View source for Category:Shay BENISTY

== Shay BENISTY ==

=== Executive Summary ===
Shay BENISTY is an inventor who has filed 25 patents. Their primary areas of innovation include {Command handling arrangements, e.g. command buffers, queues, command scheduling} (12 patents), {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} (10 patents), {Single storage device} (6 patents), and they have worked with companies such as Western Digital Technologies, Inc. (25 patents). Their most frequent collaborators include [[Category:Amir SEGEV|Amir SEGEV]] (9 collaborations), [[Category:Judah Gamliel HAHN|Judah Gamliel HAHN]] (6 collaborations), [[Category:Ariel NAVON|Ariel NAVON]] (5 collaborations).

=== Patent Filing Activity ===
[[File:Shay_BENISTY_Monthly_Patent_Applications.png|border|800px]]

=== Technology Areas ===
[[File:Shay_BENISTY_Top_Technology_Areas.png|border|800px]]

==== List of Technology Areas ====
* [[:Category:CPC_G06F3/0659|G06F3/0659]] ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 12 patents
* [[:Category:CPC_G06F3/0679|G06F3/0679]] ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 10 patents
* [[:Category:CPC_G06F3/0673|G06F3/0673]] ({Single storage device}): 6 patents
* [[:Category:CPC_G06F3/0611|G06F3/0611]] ({in relation to response time}): 5 patents
* [[:Category:CPC_G06F3/0604|G06F3/0604]] (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 4 patents
* [[:Category:CPC_G06F3/0656|G06F3/0656]] ({Data buffering arrangements}): 4 patents
* [[:Category:CPC_G06F3/061|G06F3/061]] (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 2 patents
* [[:Category:CPC_G06F3/0652|G06F3/0652]] ({Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}): 2 patents
* [[:Category:CPC_G06F3/0625|G06F3/0625]] ({Power saving in storage systems}): 2 patents
* [[:Category:CPC_G06F2213/0026|G06F2213/0026]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 2 patents
* [[:Category:CPC_G06F3/0629|G06F3/0629]] ({Configuration or reconfiguration of storage systems}): 1 patents
* [[:Category:CPC_G06F3/0631|G06F3/0631]] ({by allocating resources to storage systems}): 1 patents
* [[:Category:CPC_G06F3/0653|G06F3/0653]] ({Monitoring storage devices or systems}): 1 patents
* [[:Category:CPC_G06F12/1081|G06F12/1081]] (for peripheral access to main memory, e.g. direct memory access [DMA]): 1 patents
* [[:Category:CPC_G06F3/0635|G06F3/0635]] ({by changing the path, e.g. traffic rerouting, path reconfiguration}): 1 patents
* [[:Category:CPC_G06F13/4282|G06F13/4282]] (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
* [[:Category:CPC_G06F12/0862|G06F12/0862]] (with prefetch): 1 patents
* [[:Category:CPC_G06F2212/602|G06F2212/602]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F12/0897|G06F12/0897]] (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
* [[:Category:CPC_G06F12/10|G06F12/10]] (Address translation): 1 patents
* [[:Category:CPC_G06F2212/1016|G06F2212/1016]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F3/0658|G06F3/0658]] ({Controller construction arrangements}): 1 patents
* [[:Category:CPC_G06F11/1048|G06F11/1048]] ({using arrangements adapted for a specific error detection or correction feature}): 1 patents
* [[:Category:CPC_G06F9/441|G06F9/441]] ({Multiboot arrangements, i.e. selecting an operating system to be loaded}): 1 patents
* [[:Category:CPC_G06F9/4881|G06F9/4881]] (Program initiating; Program switching, e.g. by interrupt): 1 patents
* [[:Category:CPC_G06F12/0802|G06F12/0802]] (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 1 patents
* [[:Category:CPC_G06F12/1027|G06F12/1027]] (using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]): 1 patents
* [[:Category:CPC_H03M13/1145|H03M13/1145]] (CODING; DECODING; CODE CONVERSION IN GENERAL  (using fluidic means): 1 patents
* [[:Category:CPC_G06F13/1689|G06F13/1689]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F11/076|G06F11/076]] (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
* [[:Category:CPC_G06F11/0745|G06F11/0745]] (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
* [[:Category:CPC_G06F11/0772|G06F11/0772]] (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
* [[:Category:CPC_G06F13/4221|G06F13/4221]] (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
* [[:Category:CPC_G06F3/0608|G06F3/0608]] ({Saving storage space on storage systems}): 1 patents
* [[:Category:CPC_G06F11/263|G06F11/263]] (Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}): 1 patents
* [[:Category:CPC_G06F11/3414|G06F11/3414]] (Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation {; Recording or statistical evaluation of user activity, e.g. usability assessment}): 1 patents
* [[:Category:CPC_G06F11/3452|G06F11/3452]] ({Performance evaluation by statistical analysis}): 1 patents
* [[:Category:CPC_G06F3/0613|G06F3/0613]] ({in relation to throughput}): 1 patents
* [[:Category:CPC_G06F12/0815|G06F12/0815]] (Cache consistency protocols): 1 patents
* [[:Category:CPC_G06F12/0804|G06F12/0804]] (with main memory updating  (): 1 patents
* [[:Category:CPC_G06F12/0855|G06F12/0855]] (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
* [[:Category:CPC_G06F12/0868|G06F12/0868]] (Data transfer between cache memory and other subsystems, e.g. storage devices or host systems): 1 patents
* [[:Category:CPC_G06F12/0871|G06F12/0871]] (Allocation or management of cache space): 1 patents
* [[:Category:CPC_G06F2212/1024|G06F2212/1024]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F2212/1032|G06F2212/1032]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F2212/1056|G06F2212/1056]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F2212/214|G06F2212/214]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F2212/312|G06F2212/312]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F2212/7203|G06F2212/7203]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_G06F3/0607|G06F3/0607]] ({by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}): 1 patents
* [[:Category:CPC_G06F12/1408|G06F12/1408]] ({by using cryptography  (for digital transmission): 1 patents
* [[:Category:CPC_G06F12/0882|G06F12/0882]] (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
* [[:Category:CPC_G06F1/3225|G06F1/3225]] (Means for saving power): 1 patents

=== Companies ===
[[File:Shay_BENISTY_Top_Companies.png|border|800px]]

==== List of Companies ====
* Western Digital Technologies, Inc.: 25 patents

=== Collaborators ===
* [[:Category:Amir SEGEV|Amir SEGEV]][[Category:Amir SEGEV]] (9 collaborations)
* [[:Category:Judah Gamliel HAHN|Judah Gamliel HAHN]][[Category:Judah Gamliel HAHN]] (6 collaborations)
* [[:Category:Ariel NAVON|Ariel NAVON]][[Category:Ariel NAVON]] (5 collaborations)
* [[:Category:Alexander BAZARSKY|Alexander BAZARSKY]][[Category:Alexander BAZARSKY]] (4 collaborations)
* [[:Category:David AVRAHAM|David AVRAHAM]][[Category:David AVRAHAM]] (2 collaborations)
* [[:Category:Elkana RICHTER|Elkana RICHTER]][[Category:Elkana RICHTER]] (1 collaborations)
* [[:Category:Yossi Yoseph HASSAN|Yossi Yoseph HASSAN]][[Category:Yossi Yoseph HASSAN]] (1 collaborations)
* [[:Category:Alon MARCU|Alon MARCU]][[Category:Alon MARCU]] (1 collaborations)
* [[:Category:Rotem SELA of Sunnyvale CA (US)|Rotem SELA of Sunnyvale CA (US)]][[Category:Rotem SELA of Sunnyvale CA (US)]] (1 collaborations)
* [[:Category:Kan Lip VUI|Kan Lip VUI]][[Category:Kan Lip VUI]] (1 collaborations)

[[Category:Shay BENISTY]]
[[Category:Inventors]]
[[Category:Inventors filing patents with Western Digital Technologies, Inc.]]