View source for Category:Jiann-Tyng TZENG

== Jiann-Tyng TZENG ==

=== Executive Summary ===
Jiann-Tyng TZENG is an inventor who has filed 13 patents. Their primary areas of innovation include {Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique} (5 patents), Floor-planning or layout, e.g. partitioning or placement (5 patents), {Geometry or} layout of the interconnection structure {( (4 patents), and they have worked with companies such as TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (10 patents), Taiwan Semiconductor Manufacturing Company, Ltd. (3 patents). Their most frequent collaborators include [[Category:Shih-Wei PENG|Shih-Wei PENG]] (10 collaborations), [[Category:Wei-Cheng LIN|Wei-Cheng LIN]] (9 collaborations), [[Category:Ching-Yu HUANG|Ching-Yu HUANG]] (4 collaborations).

=== Patent Filing Activity ===
[[File:Jiann-Tyng_TZENG_Monthly_Patent_Applications.png|border|800px]]

=== Technology Areas ===
[[File:Jiann-Tyng_TZENG_Top_Technology_Areas.png|border|800px]]

==== List of Technology Areas ====
* [[:Category:CPC_H01L27/0207|H01L27/0207]] ({Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique}): 5 patents
* [[:Category:CPC_G06F30/392|G06F30/392]] (Floor-planning or layout, e.g. partitioning or placement): 5 patents
* [[:Category:CPC_H01L23/528|H01L23/528]] ({Geometry or} layout of the interconnection structure {(): 4 patents
* [[:Category:CPC_H01L23/5226|H01L23/5226]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
* [[:Category:CPC_G06F30/398|G06F30/398]] (Circuit design at the physical level  (physical level design for reconfigurable circuits): 2 patents
* [[:Category:CPC_G06F30/394|G06F30/394]] (Circuit design at the physical level  (physical level design for reconfigurable circuits): 2 patents
* [[:Category:CPC_H01L21/76877|H01L21/76877]] ({Thin films associated with contacts of capacitors}): 2 patents
* [[:Category:CPC_H01L23/5386|H01L23/5386]] (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates  ({): 2 patents
* [[:Category:CPC_H01L27/092|H01L27/092]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_G06F30/39|G06F30/39]] (Circuit design at the physical level  (physical level design for reconfigurable circuits): 1 patents
* [[:Category:CPC_H01L27/11807|H01L27/11807]] (Masterslice integrated circuits): 1 patents
* [[:Category:CPC_H01L2027/11875|H01L2027/11875]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L21/76802|H01L21/76802]] (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
* [[:Category:CPC_H01L21/38|H01L21/38]] (Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions): 1 patents
* [[:Category:CPC_H01L21/768|H01L21/768]] (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
* [[:Category:CPC_G03F1/42|G03F1/42]] (PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR;  (phototypographic composing devices): 1 patents
* [[:Category:CPC_H01L23/5384|H01L23/5384]] ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors  (): 1 patents
* [[:Category:CPC_H01L21/486|H01L21/486]] (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
* [[:Category:CPC_H03K3/0372|H03K3/0372]] (PULSE TECHNIQUE  (measuring pulse characteristics): 1 patents
* [[:Category:CPC_G06F2119/18|G06F2119/18]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
* [[:Category:CPC_H01L21/76804|H01L21/76804]] ({by forming tapered via holes}): 1 patents
* [[:Category:CPC_G11C5/14|G11C5/14]] (Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels}): 1 patents
* [[:Category:CPC_G11C5/06|G11C5/06]] (STATIC STORES  (semiconductor memory devices): 1 patents
* [[:Category:CPC_H01L23/50|H01L23/50]] (for integrated circuit devices, {e.g. power bus, number of leads} (): 1 patents
* [[:Category:CPC_H01L27/0922|H01L27/0922]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L29/0669|H01L29/0669]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L29/0847|H01L29/0847]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L29/1029|H01L29/1029]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L29/66545|H01L29/66545]] ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 1 patents
* [[:Category:CPC_H01L21/823814|H01L21/823814]] (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
* [[:Category:CPC_H01L21/823871|H01L21/823871]] (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
* [[:Category:CPC_H03K19/17744|H03K19/17744]] (PULSE TECHNIQUE  (measuring pulse characteristics): 1 patents

=== Companies ===
[[File:Jiann-Tyng_TZENG_Top_Companies.png|border|800px]]

==== List of Companies ====
* TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 10 patents
* Taiwan Semiconductor Manufacturing Company, Ltd.: 3 patents

=== Collaborators ===
* [[:Category:Shih-Wei PENG|Shih-Wei PENG]][[Category:Shih-Wei PENG]] (10 collaborations)
* [[:Category:Wei-Cheng LIN|Wei-Cheng LIN]][[Category:Wei-Cheng LIN]] (9 collaborations)
* [[:Category:Ching-Yu HUANG|Ching-Yu HUANG]][[Category:Ching-Yu HUANG]] (4 collaborations)
* [[:Category:Wei-An LAI|Wei-An LAI]][[Category:Wei-An LAI]] (3 collaborations)
* [[:Category:Chun-Yen LIN|Chun-Yen LIN]][[Category:Chun-Yen LIN]] (2 collaborations)
* [[:Category:Te-Hsin CHIU|Te-Hsin CHIU]][[Category:Te-Hsin CHIU]] (2 collaborations)
* [[:Category:Chia-Tien WU|Chia-Tien WU]][[Category:Chia-Tien WU]] (2 collaborations)
* [[:Category:Kam-Tou SIO|Kam-Tou SIO]][[Category:Kam-Tou SIO]] (2 collaborations)
* [[:Category:Wei-Cheng TZENG|Wei-Cheng TZENG]][[Category:Wei-Cheng TZENG]] (1 collaborations)
* [[:Category:Szuya LIAO|Szuya LIAO]][[Category:Szuya LIAO]] (1 collaborations)
* [[:Category:Jui-Chien HUANG|Jui-Chien HUANG]][[Category:Jui-Chien HUANG]] (1 collaborations)
* [[:Category:Cheng-Yin WANG|Cheng-Yin WANG]][[Category:Cheng-Yin WANG]] (1 collaborations)
* [[:Category:Ting-Yun WU|Ting-Yun WU]][[Category:Ting-Yun WU]] (1 collaborations)
* [[:Category:Chih-Liang CHEN|Chih-Liang CHEN]][[Category:Chih-Liang CHEN]] (1 collaborations)
* [[:Category:Charles Chew-Yuen YOUNG|Charles Chew-Yuen YOUNG]][[Category:Charles Chew-Yuen YOUNG]] (1 collaborations)
* [[:Category:Hui-Zhong ZHUANG|Hui-Zhong ZHUANG]][[Category:Hui-Zhong ZHUANG]] (1 collaborations)
* [[:Category:Shun Li CHEN|Shun Li CHEN]][[Category:Shun Li CHEN]] (1 collaborations)
* [[:Category:Jiun-Wei LU|Jiun-Wei LU]][[Category:Jiun-Wei LU]] (1 collaborations)
* [[:Category:Chih-Min HSIAO|Chih-Min HSIAO]][[Category:Chih-Min HSIAO]] (1 collaborations)
* [[:Category:Ching-Hsu CHANG|Ching-Hsu CHANG]][[Category:Ching-Hsu CHANG]] (1 collaborations)
* [[:Category:Hui-Ting YANG|Hui-Ting YANG]][[Category:Hui-Ting YANG]] (1 collaborations)
* [[:Category:Lipen YUAN|Lipen YUAN]][[Category:Lipen YUAN]] (1 collaborations)

[[Category:Jiann-Tyng TZENG]]
[[Category:Inventors]]
[[Category:Inventors filing patents with TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.]]
[[Category:Inventors filing patents with Taiwan Semiconductor Manufacturing Company, Ltd.]]