Category:Chi On Chui: Difference between revisions

Chi On Chui

Executive Summary

Chi On Chui is an inventor who has filed 16 patents. Their primary areas of innovation include {using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate} (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Co., Ltd. (16 patents). Their most frequent collaborators include (3 collaborations), (3 collaborations), (3 collaborations).

Patent Filing Activity

File:Chi On Chui Monthly Patent Applications.png

Technology Areas

File:Chi On Chui Top Technology Areas.png

List of Technology Areas

• H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 4 patents
• H01L29/66795 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L21/823431 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 3 patents
• H01L21/823807 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 3 patents
• H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H10D84/038 (No explanation available): 3 patents
• H10D30/6735 (No explanation available): 3 patents
• H10D62/121 (No explanation available): 3 patents
• H10B51/20 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B51/10 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B53/20 (ELECTRONIC MEMORY DEVICES): 2 patents
• H01L21/28123 ({Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects}): 2 patents
• H01L21/02164 ({the material being a silicon oxide, e.g. SiO): 2 patents
• H01L21/31053 ({involving a dielectric removal step}): 2 patents
• H01L21/823814 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L27/0924 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/0847 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/7848 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/7851 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/31111 ({by chemical means}): 2 patents
• H01L29/785 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/6656 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 2 patents
• H01L29/66742 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L27/0922 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H10D30/6219 (No explanation available): 2 patents
• H10D30/62 (No explanation available): 2 patents
• H10D30/014 (No explanation available): 2 patents
• H10D30/43 (No explanation available): 2 patents
• H10D30/6757 (No explanation available): 2 patents
• H10D64/017 (No explanation available): 2 patents
• H01L29/7869 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/02238 ({the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers): 1 patents
• H01L21/02274 ({the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers): 1 patents
• H01L21/0228 ({deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD}): 1 patents
• H01L21/76227 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers}): 1 patents
• H01L21/823821 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823828 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823878 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/0653 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66636 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/823481 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/0217 ({the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz (): 1 patents
• H01L21/31116 ({by dry-etching}): 1 patents
• H01L21/762 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers}): 1 patents
• H01L21/764 (Making of isolation regions between components): 1 patents
• H01L21/823437 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/0886 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/0649 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/6653 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• H01L21/8258 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/8221 ({Three dimensional integrated circuits stacked in different levels}): 1 patents
• H01L21/823857 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/516 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66553 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• G11C5/063 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C11/223 ({using MOS with ferroelectric gate insulating film}): 1 patents
• H01L29/40111 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/40117 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B43/10 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B43/20 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L29/0665 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/324 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823418 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/78618 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10D30/024 (No explanation available): 1 patents
• H10D84/0158 (No explanation available): 1 patents
• H01L21/28088 (Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups): 1 patents
• H10D62/118 (No explanation available): 1 patents
• H10D62/292 (No explanation available): 1 patents
• H10D64/667 (No explanation available): 1 patents
• H01L21/28185 ({with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor}): 1 patents
• H01L21/823456 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823462 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/088 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/42376 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/02433 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10D62/151 (No explanation available): 1 patents
• H10D62/40 (No explanation available): 1 patents
• H10D84/0167 (No explanation available): 1 patents
• H10D84/017 (No explanation available): 1 patents
• H10D84/85 (No explanation available): 1 patents
• H10D64/021 (No explanation available): 1 patents
• H10D84/0135 (No explanation available): 1 patents
• H10D84/0147 (No explanation available): 1 patents
• H10D84/83 (No explanation available): 1 patents
• H01L29/41791 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2029/7857 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• G03F7/094 (characterised by structural details, e.g. supports, auxiliary layers (supports for printing plates in general): 1 patents
• G03F7/16 (Coating processes; Apparatus therefor (applying coatings to base materials in general): 1 patents
• G03F7/2004 (Exposure; Apparatus therefor (photographic printing apparatus for making copies): 1 patents
• G03F7/26 (Processing photosensitive materials; Apparatus therefor (): 1 patents
• H01L21/0274 (Making masks on semiconductor bodies for further photolithographic processing not provided for in group): 1 patents
• H01L21/31144 ({using masks}): 1 patents

Companies

File:Chi On Chui Top Companies.png

List of Companies

• Taiwan Semiconductor Manufacturing Co., Ltd.: 16 patents

Collaborators

• Sai-Hooi Yeong (3 collaborations)
• Tai-Chun Huang (3 collaborations)
• Shu-Han Chen (3 collaborations)
• Hsin-Yi Lee (3 collaborations)
• Ting-Gang Chen (2 collaborations)
• Yung-Cheng Lu (2 collaborations)
• Cheng-Yu Wei (2 collaborations)
• Hao-Ming Tang (2 collaborations)
• Cheng-I Lin (2 collaborations)
• Weng Chang (2 collaborations)
• Cheng-Lung Hung (2 collaborations)
• Bo-Feng Young (1 collaborations)
• Yu-Ming Lin (1 collaborations)
• Ya-Lan Chang (1 collaborations)
• Chieh-Ping Wang (1 collaborations)
• Bo-Cyuan Lu (1 collaborations)
• Wan-Yi Kao (1 collaborations)
• Hung Cheng Lin (1 collaborations)
• Chunyao Wang (1 collaborations)
• Yen-Jui Chiu (1 collaborations)
• Te-Yang Lai (1 collaborations)
• An Lee (1 collaborations)
• Jyun-Yi Wu (1 collaborations)
• Da-Yuan Lee (1 collaborations)
• Sheng-Chen Wang (1 collaborations)
• Hsiang-Pi Chang (1 collaborations)
• Huang-Lin Chao of Hillsboro OR (US) (1 collaborations)
• Chung-Liang Cheng (1 collaborations)
• Kun-Yu Lee (1 collaborations)
• Tzer-Min Shen (1 collaborations)
• Yen-Tien Tung (1 collaborations)
• Chun-I Wu (1 collaborations)
• Ming-Ho Lin (1 collaborations)
• Chun-Heng Chen (1 collaborations)
• Xiong-Fei Yu (1 collaborations)
• Meng-Han Lin (1 collaborations)
• Chen-Fong Tsai (1 collaborations)
• Han-De Chen (1 collaborations)
• Yu-Chang Lin (1 collaborations)
• Liang-Yin Chen (1 collaborations)
• Liang-Yi Chang (1 collaborations)