Category:Hung-Jui Kuo: Difference between revisions
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=== Executive Summary === | === Executive Summary === | ||
Hung-Jui Kuo is an inventor who has filed | Hung-Jui Kuo is an inventor who has filed 7 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups (2 patents), Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups (2 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Company, Ltd. (7 patents). Their most frequent collaborators include [[Category:Hui-Jung Tsai|Hui-Jung Tsai]] (3 collaborations), [[Category:Ming-Che Ho|Ming-Che Ho]] (2 collaborations), [[Category:Tai-Min Chang|Tai-Min Chang]] (2 collaborations). | ||
=== Patent Filing Activity === | === Patent Filing Activity === | ||
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==== List of Technology Areas ==== | ==== List of Technology Areas ==== | ||
* [[:Category: | * [[:Category:CPC_H01L23/3128|H01L23/3128]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents | ||
* [[:Category:CPC_H01L21/ | * [[:Category:CPC_H01L21/4853|H01L21/4853]] (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 2 patents | ||
* [[:Category:CPC_H01L21/ | * [[:Category:CPC_H01L21/4857|H01L21/4857]] (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 2 patents | ||
* [[:Category:CPC_H01L21/565|H01L21/565]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | |||
* [[:Category:CPC_H01L23/5383|H01L23/5383]] ({Multilayer substrates (): 2 patents | |||
* [[:Category: | * [[:Category:CPC_H01L23/5386|H01L23/5386]] (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 2 patents | ||
* [[:Category: | * [[:Category:CPC_H01L23/5389|H01L23/5389]] (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 2 patents | ||
* [[:Category:CPC_H01L24/19|H01L24/19]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | |||
* [[:Category:CPC_H01L23/ | |||
* [[:Category:CPC_H01L23/ | |||
* [[:Category: | |||
* [[:Category:CPC_H01L24/20|H01L24/20]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | * [[:Category:CPC_H01L24/20|H01L24/20]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | ||
* [[:Category: | * [[:Category:CPC_H01L2224/214|H01L2224/214]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | ||
* [[:Category: | * [[:Category:CPC_H01L21/568|H01L21/568]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | ||
* [[:Category: | * [[:Category:CPC_H01L21/56|H01L21/56]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | ||
* [[:Category: | * [[:Category:CPC_H01L23/31|H01L23/31]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents | ||
* [[:Category:CPC_H01L23/ | * [[:Category:CPC_H01L23/528|H01L23/528]] ({Geometry or} layout of the interconnection structure {(): 2 patents | ||
* [[:Category:CPC_H01L23/49822|H01L23/49822]] ({Multilayer substrates (multilayer metallisation on monolayer substrate): 2 patents | * [[:Category:CPC_H01L23/49822|H01L23/49822]] ({Multilayer substrates (multilayer metallisation on monolayer substrate): 2 patents | ||
* [[:Category:CPC_H01L23/564|H01L23/564]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L23/ | * [[:Category:CPC_H01L2924/364|H01L2924/364]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category: | * [[:Category:CPC_G03F7/426|G03F7/426]] ({containing organic halogen compounds; containing organic sulfonic acids or salts thereof; containing sulfoxides}): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H01L21/4864|H01L21/4864]] (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents | ||
* [[:Category:CPC_H01L21/ | * [[:Category:CPC_H01L21/6835|H01L21/6835]] ({using temporarily an auxiliary support}): 1 patents | ||
* [[:Category:CPC_H01L2221/68372|H01L2221/68372]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L23/5226|H01L23/5226]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L21/ | |||
* [[:Category:CPC_H01L2221/ | |||
* [[:Category: | |||
* [[:Category:CPC_H01L21/76802|H01L21/76802]] (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents | * [[:Category:CPC_H01L21/76802|H01L21/76802]] (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H01L21/78|H01L21/78]] (with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 1 patents | ||
* [[:Category:CPC_H01L21/76898|H01L21/76898]] ({formed through a semiconductor substrate}): 1 patents | * [[:Category:CPC_H01L21/76898|H01L21/76898]] ({formed through a semiconductor substrate}): 1 patents | ||
* [[:Category:CPC_H01L21/76804|H01L21/76804]] ({by forming tapered via holes}): 1 patents | * [[:Category:CPC_H01L21/76804|H01L21/76804]] ({by forming tapered via holes}): 1 patents | ||
* [[:Category:CPC_H01L21/76846|H01L21/76846]] ({Layer combinations}): 1 patents | * [[:Category:CPC_H01L21/76846|H01L21/76846]] ({Layer combinations}): 1 patents | ||
* [[:Category:CPC_H01L21/76871|H01L21/76871]] ({Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers}): 1 patents | |||
* [[:Category:CPC_H01L23/481|H01L23/481]] (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 1 patents | |||
* [[:Category:CPC_H01L25/105|H01L25/105]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L23/49816|H01L23/49816]] (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents | |||
* [[:Category:CPC_H01L23/49838|H01L23/49838]] (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents | |||
* [[:Category:CPC_H01L2225/1041|H01L2225/1041]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | * [[:Category:CPC_H01L2225/1041|H01L2225/1041]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H01L24/14|H01L24/14]] ({of a plurality of bump connectors}): 1 patents | ||
* [[:Category:CPC_H01L25/ | * [[:Category:CPC_H01L25/50|H01L25/50]] ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 1 patents | ||
* [[:Category:CPC_H01L24/82|H01L24/82]] ({by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] (interconnection structure between a plurality of semiconductor chips): 1 patents | * [[:Category:CPC_H01L24/82|H01L24/82]] ({by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] (interconnection structure between a plurality of semiconductor chips): 1 patents | ||
* [[:Category:CPC_H01L23/5384|H01L23/5384]] ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents | * [[:Category:CPC_H01L23/5384|H01L23/5384]] ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents | ||
* [[:Category:CPC_H01L24/80|H01L24/80]] ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents | |||
* [[:Category:CPC_H01L24/ | |||
* [[:Category:CPC_H01L24/95|H01L24/95]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | * [[:Category:CPC_H01L24/95|H01L24/95]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H01L25/0657|H01L25/0657]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H10D88/00|H10D88/00]] (No explanation available): 1 patents | ||
* [[:Category:CPC_H01L2224/ | * [[:Category:CPC_H01L2224/80896|H01L2224/80896]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H01L24/13|H01L24/13]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H01L24/32|H01L24/32]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category: | * [[:Category:CPC_H01L25/0655|H01L25/0655]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | ||
* [[:Category:CPC_H01L2224/13007|H01L2224/13007]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L2224/32146|H01L2224/32146]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L2224/32235|H01L2224/32235]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L2924/15311|H01L2924/15311]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L2924/182|H01L2924/182]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents | |||
* [[:Category:CPC_H01L2224/ | |||
* [[:Category:CPC_H01L2224/ | |||
* [[:Category:CPC_H01L2224/ | |||
* [[:Category: | |||
* [[:Category: | |||
=== Companies === | === Companies === | ||
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==== List of Companies ==== | ==== List of Companies ==== | ||
* Taiwan Semiconductor Manufacturing Company, Ltd.: | * Taiwan Semiconductor Manufacturing Company, Ltd.: 7 patents | ||
=== Collaborators === | === Collaborators === | ||
* [[:Category: | * [[:Category:Hui-Jung Tsai|Hui-Jung Tsai]][[Category:Hui-Jung Tsai]] (3 collaborations) | ||
* [[:Category:Ming-Che Ho|Ming-Che Ho]][[Category:Ming-Che Ho]] (2 collaborations) | |||
* [[:Category:Ming-Che Ho|Ming-Che Ho]][[Category:Ming-Che Ho]] ( | * [[:Category:Tai-Min Chang|Tai-Min Chang]][[Category:Tai-Min Chang]] (2 collaborations) | ||
* [[:Category: | * [[:Category:Meng-Che Tu|Meng-Che Tu]][[Category:Meng-Che Tu]] (2 collaborations) | ||
* [[:Category:Yu-Hsiang Hu|Yu-Hsiang Hu]][[Category:Yu-Hsiang Hu]] (2 collaborations) | |||
* [[:Category:Chia-Wei Wang|Chia-Wei Wang]][[Category:Chia-Wei Wang]] (2 collaborations) | |||
* [[:Category:Meng-Che Tu|Meng-Che Tu]][[Category:Meng-Che Tu]] ( | |||
* [[:Category: | |||
* [[:Category: | |||
* [[:Category:Ching-Wen Chen|Ching-Wen Chen]][[Category:Ching-Wen Chen]] (1 collaborations) | * [[:Category:Ching-Wen Chen|Ching-Wen Chen]][[Category:Ching-Wen Chen]] (1 collaborations) | ||
* [[:Category: | * [[:Category:Sih-Hao Liao|Sih-Hao Liao]][[Category:Sih-Hao Liao]] (1 collaborations) | ||
* [[:Category: | * [[:Category:Wei-Chung Chang|Wei-Chung Chang]][[Category:Wei-Chung Chang]] (1 collaborations) | ||
* [[:Category:Yu-Tzu Chang|Yu-Tzu Chang]][[Category:Yu-Tzu Chang]] (1 collaborations) | |||
* [[:Category:Po-Han Wang|Po-Han Wang]][[Category:Po-Han Wang]] (1 collaborations) | |||
* [[:Category: | |||
* [[:Category: | |||
[[Category:Hung-Jui Kuo]] | [[Category:Hung-Jui Kuo]] | ||
[[Category:Inventors]] | [[Category:Inventors]] | ||
[[Category:Inventors filing patents with Taiwan Semiconductor Manufacturing Company, Ltd.]] | [[Category:Inventors filing patents with Taiwan Semiconductor Manufacturing Company, Ltd.]] |
Revision as of 03:44, 28 March 2025
Hung-Jui Kuo
Executive Summary
Hung-Jui Kuo is an inventor who has filed 7 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups (2 patents), Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups (2 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Company, Ltd. (7 patents). Their most frequent collaborators include (3 collaborations), (2 collaborations), (2 collaborations).
Patent Filing Activity
File:Hung-Jui Kuo Monthly Patent Applications.png
Technology Areas
File:Hung-Jui Kuo Top Technology Areas.png
List of Technology Areas
- H01L23/3128 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
- H01L21/4853 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 2 patents
- H01L21/4857 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 2 patents
- H01L21/565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L23/5383 ({Multilayer substrates (): 2 patents
- H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 2 patents
- H01L23/5389 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 2 patents
- H01L24/19 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L24/20 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L2224/214 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L21/568 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L21/56 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L23/31 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L23/528 ({Geometry or} layout of the interconnection structure {(): 2 patents
- H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 2 patents
- H01L23/564 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/364 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- G03F7/426 ({containing organic halogen compounds; containing organic sulfonic acids or salts thereof; containing sulfoxides}): 1 patents
- H01L21/4864 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
- H01L21/6835 ({using temporarily an auxiliary support}): 1 patents
- H01L2221/68372 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
- H01L21/78 (with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 1 patents
- H01L21/76898 ({formed through a semiconductor substrate}): 1 patents
- H01L21/76804 ({by forming tapered via holes}): 1 patents
- H01L21/76846 ({Layer combinations}): 1 patents
- H01L21/76871 ({Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers}): 1 patents
- H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 1 patents
- H01L25/105 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L23/49838 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L2225/1041 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/14 ({of a plurality of bump connectors}): 1 patents
- H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 1 patents
- H01L24/82 ({by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] (interconnection structure between a plurality of semiconductor chips): 1 patents
- H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
- H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents
- H01L24/95 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H10D88/00 (No explanation available): 1 patents
- H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/13 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/13007 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/32146 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/32235 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/15311 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/182 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
Companies
File:Hung-Jui Kuo Top Companies.png
List of Companies
- Taiwan Semiconductor Manufacturing Company, Ltd.: 7 patents
Collaborators
- Hui-Jung Tsai (3 collaborations)
- Ming-Che Ho (2 collaborations)
- Tai-Min Chang (2 collaborations)
- Meng-Che Tu (2 collaborations)
- Yu-Hsiang Hu (2 collaborations)
- Chia-Wei Wang (2 collaborations)
- Ching-Wen Chen (1 collaborations)
- Sih-Hao Liao (1 collaborations)
- Wei-Chung Chang (1 collaborations)
- Yu-Tzu Chang (1 collaborations)
- Po-Han Wang (1 collaborations)