Category:Shin-Puu Jeng: Difference between revisions

Shin-Puu Jeng

Executive Summary

Shin-Puu Jeng is an inventor who has filed 4 patents. Their primary areas of innovation include {Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group (3 patents), {Multilayer substrates (multilayer metallisation on monolayer substrate (2 patents), Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups (2 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Co., Ltd. (4 patents). Their most frequent collaborators include (3 collaborations), (2 collaborations), (2 collaborations).

Patent Filing Activity

File:Shin-Puu Jeng Monthly Patent Applications.png

Technology Areas

File:Shin-Puu Jeng Top Technology Areas.png

List of Technology Areas

• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 3 patents
• H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 2 patents
• H01L21/486 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 2 patents
• H01L21/568 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/3128 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/0231 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/02331 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/4857 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 2 patents
• H01L21/56 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/561 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/6835 ({using temporarily an auxiliary support}): 1 patents
• H01L23/3114 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L23/49894 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L24/03 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/11 ({Manufacturing methods (for bumps on insulating substrates): 1 patents
• H01L24/13 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/19 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/81 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/96 ({the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting}): 1 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68359 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68372 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/02379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/18 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/18161 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/24 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/25 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 1 patents
• H01L2224/0235 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/24137 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/24155 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/2505 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/25171 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5383 ({Multilayer substrates (): 1 patents
• H01L23/28 (Encapsulations, e.g. encapsulating layers, coatings, {e.g. for protection} (): 1 patents
• H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
• H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 1 patents
• H01L23/552 (Protection against radiation, e.g. light {or electromagnetic waves}): 1 patents
• H01L21/4853 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
• H01L21/565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49838 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/3025 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

File:Shin-Puu Jeng Top Companies.png

List of Companies

• Taiwan Semiconductor Manufacturing Co., Ltd.: 4 patents

Collaborators

• Po-Yao Chuang (3 collaborations)
• Po-Hao Tsai (2 collaborations)
• Techi Wong (2 collaborations)
• Yi-Wen Wu (1 collaborations)
• Meng-Liang Lin (1 collaborations)
• Shih-Ting Hung (1 collaborations)
• Monsen Liu (1 collaborations)
• Shuo-Mao Chen (1 collaborations)
• Hsien-Wei Chen (1 collaborations)
• Meng-Wei Chou (1 collaborations)