Category:Rajesh KATKAR of Milpitas CA (US): Difference between revisions

Latest revision as of 11:02, 31 March 2025

Rajesh KATKAR of Milpitas CA (US)

Executive Summary

Rajesh KATKAR of Milpitas CA (US) is an inventor who has filed 2 patents. Their primary areas of innovation include Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate (1 patents), {Multilayer substrates (multilayer metallisation on monolayer substrate (1 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (1 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (2 patents). Their most frequent collaborators include (2 collaborations).

Patent Filing Activity

File:Rajesh KATKAR of Milpitas CA (US) Monthly Patent Applications.png

Technology Areas

File:Rajesh KATKAR of Milpitas CA (US) Top Technology Areas.png

List of Technology Areas

H01L23/49838 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 1 patents
H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L24/45 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05024 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05025 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/45005 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/4502 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/01014 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/01029 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/1427 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/1432 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

File:Rajesh KATKAR of Milpitas CA (US) Top Companies.png

List of Companies

ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.: 2 patents

Collaborators

Xu CHANG of San Jose CA (US) (2 collaborations)

Subcategories

This category has the following 2 subcategories, out of 2 total.

R

► Rajesh KATKAR of Milpitas CA (US)‎ (2 C)

X

► Xu CHANG of San Jose CA (US)‎ (2 C)

@@ Line 2: / Line 2: @@
 === Executive Summary ===
-Rajesh KATKAR of Milpitas CA (US) is an inventor who has filed 2 patents. Their primary areas of innovation include {Geometry or} layout of the interconnection structure {( (1 patents), {Foil-like cooling fins or heat sinks  (being part of lead-frames (1 patents), Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers  (shape of the substrate (1 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (2 patents). Their most frequent collaborators include [[Category:Belgacem HABA of Saratoga CA (US)|Belgacem HABA of Saratoga CA (US)]] (1 collaborations), [[Category:Cyprian Emeka UZOH of San Jose CA (US)|Cyprian Emeka UZOH of San Jose CA (US)]] (1 collaborations), [[Category:Xu CHANG of San Jose CA (US)|Xu CHANG of San Jose CA (US)]] (1 collaborations).
+Rajesh KATKAR of Milpitas CA (US) is an inventor who has filed 2 patents. Their primary areas of innovation include Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers  (shape of the substrate (1 patents), {Multilayer substrates  (multilayer metallisation on monolayer substrate (1 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (1 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (2 patents). Their most frequent collaborators include [[Category:Xu CHANG of San Jose CA (US)|Xu CHANG of San Jose CA (US)]] (2 collaborations).
 === Patent Filing Activity ===
@@ Line 11: / Line 11: @@
 ==== List of Technology Areas ====
-* [[:Category:CPC_H01L23/5286|H01L23/5286]] ({Geometry or} layout of the interconnection structure {(): 1 patents
+* [[:Category:CPC_H01L23/49838|H01L23/49838]] (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers  (shape of the substrate): 1 patents
-* [[:Category:CPC_H01L23/3672|H01L23/3672]] ({Foil-like cooling fins or heat sinks  (being part of lead-frames): 1 patents
-* [[:Category:CPC_H01L23/49816|H01L23/49816]] (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers  (shape of the substrate): 1 patents
 * [[:Category:CPC_H01L23/49822|H01L23/49822]] ({Multilayer substrates  (multilayer metallisation on monolayer substrate): 1 patents
 * [[:Category:CPC_H01L24/05|H01L24/05]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L24/13|H01L24/13]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L24/45|H01L24/45]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L25/0657|H01L25/0657]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L25/0652|H01L25/0652]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2224/05009|H01L2224/05009]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L2224/05024|H01L2224/05024]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
 * [[:Category:CPC_H01L2224/05025|H01L2224/05025]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2224/13007|H01L2224/13007]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L2224/45005|H01L2224/45005]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2224/13026|H01L2224/13026]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L2224/4502|H01L2224/4502]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2225/06513|H01L2225/06513]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L2924/01014|H01L2924/01014]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2225/06527|H01L2225/06527]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
 * [[:Category:CPC_H01L2924/01029|H01L2924/01029]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
 * [[:Category:CPC_H01L2924/1427|H01L2924/1427]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2924/1431|H01L2924/1431]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L2924/1432|H01L2924/1432]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2924/15311|H01L2924/15311]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H01L23/528|H01L23/528]] ({Geometry or} layout of the interconnection structure {(): 1 patents
-* [[:Category:CPC_H01L23/544|H01L23/544]] (Marks applied to semiconductor devices {or parts}, e.g. registration marks, {alignment structures, wafer maps  (test patterns for characterising or monitoring manufacturing processes): 1 patents
-* [[:Category:CPC_H01L21/6835|H01L21/6835]] ({using temporarily an auxiliary support}): 1 patents
-* [[:Category:CPC_H01L21/78|H01L21/78]] (with subsequent division of the substrate into plural individual devices  (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 1 patents
 * [[:Category:CPC_H01L24/08|H01L24/08]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L24/80|H01L24/80]] ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents
+* [[:Category:CPC_H01L25/0657|H01L25/0657]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2223/5446|H01L2223/5446]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
 * [[:Category:CPC_H01L2224/08145|H01L2224/08145]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2224/80895|H01L2224/80895]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2224/80896|H01L2224/80896]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
 === Companies ===
@@ Line 45: / Line 36: @@
 === Collaborators ===
-* [[:Category:Belgacem HABA of Saratoga CA (US)|Belgacem HABA of Saratoga CA (US)]][[Category:Belgacem HABA of Saratoga CA (US)]] (1 collaborations)
+* [[:Category:Xu CHANG of San Jose CA (US)|Xu CHANG of San Jose CA (US)]][[Category:Xu CHANG of San Jose CA (US)]] (2 collaborations)
-* [[:Category:Cyprian Emeka UZOH of San Jose CA (US)|Cyprian Emeka UZOH of San Jose CA (US)]][[Category:Cyprian Emeka UZOH of San Jose CA (US)]] (1 collaborations)
-* [[:Category:Xu CHANG of San Jose CA (US)|Xu CHANG of San Jose CA (US)]][[Category:Xu CHANG of San Jose CA (US)]] (1 collaborations)
 [[Category:Rajesh KATKAR of Milpitas CA (US)]]
 [[Category:Inventors]]
 [[Category:Inventors filing patents with ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.]]