Category:Kuo-Cheng CHIANG

Kuo-Cheng CHIANG

Executive Summary

Kuo-Cheng CHIANG is an inventor who has filed 7 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (6 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Co., Ltd. (7 patents). Their most frequent collaborators include (7 collaborations), (3 collaborations), (3 collaborations).

Patent Filing Activity

File:Kuo-Cheng CHIANG Monthly Patent Applications.png

Technology Areas

File:Kuo-Cheng CHIANG Top Technology Areas.png

List of Technology Areas

• H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 6 patents
• H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/41775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/76224 ({using trench refilling with dielectric materials (trench filling with polycristalline silicon): 2 patents
• H01L27/088 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/0665 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/66742 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/823807 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823828 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/0653 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/764 (Making of isolation regions between components): 1 patents
• H01L29/0847 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 1 patents
• H01L21/76229 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers}): 1 patents
• H01L29/4175 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66553 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• H01L21/28123 ({Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects}): 1 patents
• H01L21/0259 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823475 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823481 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823468 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/41733 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/42364 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/4238 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/6656 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• H01L29/78618 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10D84/834 (No explanation available): 1 patents
• H10D30/0243 (No explanation available): 1 patents
• H10D30/6211 (No explanation available): 1 patents
• H10D30/6215 (No explanation available): 1 patents
• H10D62/118 (No explanation available): 1 patents
• H10D84/0128 (No explanation available): 1 patents
• H10D84/0158 (No explanation available): 1 patents
• H10D84/038 (No explanation available): 1 patents

Companies

File:Kuo-Cheng CHIANG Top Companies.png

List of Companies

• Taiwan Semiconductor Manufacturing Co., Ltd.: 7 patents

Collaborators

• Chih-Hao WANG (7 collaborations)
• Chia-Hao CHANG (3 collaborations)
• Jia-Chuan YOU (3 collaborations)
• Chu-Yuan HSU (2 collaborations)
• Chung-Wei HSU (1 collaborations)
• Lung-Kun CHU (1 collaborations)
• Jia-Ni YU (1 collaborations)
• Chun-Fu LU (1 collaborations)
• Shih-Hao LAI (1 collaborations)
• Jung-Hung CHANG (1 collaborations)
• Shih-Cheng CHEN (1 collaborations)
• Chia-Hao YU (1 collaborations)
• Chia-Cheng TSAI (1 collaborations)
• Hsien-Chih HUANG (1 collaborations)
• Guan-Lin CHEN (1 collaborations)
• Shi Ning JU (1 collaborations)
• Lo-Heng CHANG (1 collaborations)
• Huan-Chieh SU (1 collaborations)
• Chun-Yuan CHEN (1 collaborations)
• Li-Yang CHUANG (1 collaborations)