Category:Rajesh KATKAR of Milpitas CA (US)

Rajesh KATKAR of Milpitas CA (US)

Executive Summary

Rajesh KATKAR of Milpitas CA (US) is an inventor who has filed 2 patents. Their primary areas of innovation include {Geometry or} layout of the interconnection structure {( (1 patents), {Foil-like cooling fins or heat sinks (being part of lead-frames (1 patents), Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate (1 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (2 patents). Their most frequent collaborators include (1 collaborations), (1 collaborations), (1 collaborations).

Patent Filing Activity

File:Rajesh KATKAR of Milpitas CA (US) Monthly Patent Applications.png

Technology Areas

File:Rajesh KATKAR of Milpitas CA (US) Top Technology Areas.png

List of Technology Areas

H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 1 patents
H01L23/3672 ({Foil-like cooling fins or heat sinks (being part of lead-frames): 1 patents
H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 1 patents
H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L24/13 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05009 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05025 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/13007 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/13026 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2225/06513 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2225/06527 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/01029 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/1427 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/1431 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/15311 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L23/544 (Marks applied to semiconductor devices {or parts}, e.g. registration marks, {alignment structures, wafer maps (test patterns for characterising or monitoring manufacturing processes): 1 patents
H01L21/6835 ({using temporarily an auxiliary support}): 1 patents
H01L21/78 (with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 1 patents
H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents
H01L2223/5446 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents