Category:Chi Yuan of San Jose CA (US)

Chi Yuan of San Jose CA (US)

Executive Summary

Chi Yuan of San Jose CA (US) is an inventor who has filed 7 patents. Their primary areas of innovation include Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing (2 patents), {Test methods} (2 patents), Tester hardware, i.e. output processing circuits {( (2 patents), and they have worked with companies such as ADVANTEST CORPORATION (7 patents). Their most frequent collaborators include (7 collaborations), (2 collaborations), (1 collaborations).

Patent Filing Activity

File:Chi Yuan of San Jose CA (US) Monthly Patent Applications.png

Technology Areas

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List of Technology Areas

• G06F11/2205 (Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing): 2 patents
• G06F11/2273 ({Test methods}): 2 patents
• G06F11/2733 (Tester hardware, i.e. output processing circuits {(): 2 patents
• G01R31/287 (Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits): 1 patents
• G06F3/0607 ({by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}): 1 patents
• G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 1 patents
• G06F11/3476 ({Data logging (): 1 patents
• G06F11/0787 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F13/4221 (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
• G06F13/4282 (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
• G06F2213/0026 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2213/0028 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F11/263 (Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}): 1 patents
• G06F11/27 (Built-in tests): 1 patents
• G06F21/53 (by executing in a restricted environment, e.g. sandbox or secure virtual machine): 1 patents
• G06F2221/034 (Indexing scheme relating to): 1 patents

Companies

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List of Companies

• ADVANTEST CORPORATION: 7 patents

Collaborators

• Srdjan Malisic of San Jose CA (US) (7 collaborations)
• Jenny Chen of San Jose CA (US) (2 collaborations)
• Rebecca Qiu of San Jose CA (US) (1 collaborations)