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Category:Chia-Ching Lin of Portland OR (US) - WikiTrademarks Jump to content

Category:Chia-Ching Lin of Portland OR (US)

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Chia-Ching Lin of Portland OR (US)

Executive Summary

Chia-Ching Lin of Portland OR (US) is an inventor who has filed 8 patents. Their primary areas of innovation include No explanation available (3 patents), No explanation available (3 patents), {Geometry or} layout of the interconnection structure {( (2 patents), and they have worked with companies such as Intel Corporation (8 patents). Their most frequent collaborators include (5 collaborations), (5 collaborations), (5 collaborations).

Patent Filing Activity

File:Chia-Ching Lin of Portland OR (US) Monthly Patent Applications.png

Technology Areas

File:Chia-Ching Lin of Portland OR (US) Top Technology Areas.png

List of Technology Areas

  • H10D30/6735 (No explanation available): 3 patents
  • H10D30/6757 (No explanation available): 3 patents
  • H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 2 patents
  • H10D84/85 (No explanation available): 2 patents
  • H10D30/014 (No explanation available): 2 patents
  • H10D62/121 (No explanation available): 2 patents
  • H01G7/06 (CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric): 1 patents
  • H01L28/57 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L28/60 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10B12/30 (ELECTRONIC MEMORY DEVICES): 1 patents
  • H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/1037 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/7845 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/7851 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10D62/115 (No explanation available): 1 patents
  • H10D30/47 (No explanation available): 1 patents
  • H10D62/118 (No explanation available): 1 patents
  • H01L23/5223 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10D1/682 (No explanation available): 1 patents
  • H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
  • H01L23/5381 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
  • H01L23/5385 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
  • H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/17 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L25/16 (the devices being of types provided for in two or more different main groups of groups): 1 patents
  • H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/17515 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/32265 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2924/1205 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H10D30/6713 (No explanation available): 1 patents
  • H01L21/02568 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/46 (Treatment of semiconductor bodies using processes or apparatus not provided for in groups): 1 patents
  • H10D48/362 (No explanation available): 1 patents
  • H10D62/80 (No explanation available): 1 patents
  • H10D64/689 (No explanation available): 1 patents
  • H10D99/00 (No explanation available): 1 patents
  • H10D30/6219 (No explanation available): 1 patents
  • H10D64/687 (No explanation available): 1 patents
  • H10D64/679 (No explanation available): 1 patents
  • H01L21/28123 ({Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects}): 1 patents
  • H01L21/7806 ({involving the separation of the active layers from a substrate}): 1 patents
  • H10D30/43 (No explanation available): 1 patents
  • H10D30/6729 (No explanation available): 1 patents
  • H10D64/017 (No explanation available): 1 patents

Companies

File:Chia-Ching Lin of Portland OR (US) Top Companies.png

List of Companies

  • Intel Corporation: 8 patents

Collaborators

Subcategories

This category has the following 2 subcategories, out of 2 total.

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