Category:Frederick A. Ware of Los Altos Hills CA (US)

Frederick A. Ware of Los Altos Hills CA (US)

Executive Summary

Frederick A. Ware of Los Altos Hills CA (US) is an inventor who has filed 9 patents. Their primary areas of innovation include Responding to the occurrence of a fault, e.g. fault tolerance (2 patents), {in relation to data integrity, e.g. data losses, bit errors} (2 patents), {in sector programmable memories, e.g. flash disk ( (2 patents), and they have worked with companies such as Rambus Inc. (8 patents), RAMBUS INC. (1 patents). Their most frequent collaborators include (2 collaborations), (2 collaborations), (1 collaborations).

Patent Filing Activity

File:Frederick A. Ware of Los Altos Hills CA (US) Monthly Patent Applications.png

Technology Areas

File:Frederick A. Ware of Los Altos Hills CA (US) Top Technology Areas.png

List of Technology Areas

• G06F11/073 (Responding to the occurrence of a fault, e.g. fault tolerance): 2 patents
• G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 2 patents
• G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 2 patents
• G06F11/20 (using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements): 2 patents
• G11C29/52 (STATIC STORES (semiconductor memory devices): 2 patents
• G06F12/0802 (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 2 patents
• G06F13/1684 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
• G06F11/1044 ({with specific ECC/EDC distribution}): 2 patents
• G06F11/1048 ({using arrangements adapted for a specific error detection or correction feature}): 2 patents
• G11C7/10 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 2 patents
• G06F3/064 ({Management of blocks}): 1 patents
• G06F3/0673 ({Single storage device}): 1 patents
• G06F11/006 ({Identification (): 1 patents
• G06F11/0745 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0766 ({Error or fault reporting or storing}): 1 patents
• G06F11/0793 ({Remedial or corrective actions (recovery from an exception in an instruction pipeline): 1 patents
• G06F11/10 (Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's): 1 patents
• G06F11/1008 ({in individual solid state devices (): 1 patents
• G06F11/1076 ({Parity data used in redundant arrays of independent storages, e.g. in RAID systems}): 1 patents
• G06F11/1402 ({Saving, restoring, recovering or retrying}): 1 patents
• G06F11/141 (Error detection or correction of the data by redundancy in operation (): 1 patents
• G06F11/1443 ({Transmit or communication errors}): 1 patents
• H03M13/03 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• H04L1/004 ({by using forward error control (): 1 patents
• H04L1/0057 ({Block codes (): 1 patents
• H04L1/0061 ({Trellis-coded modulation}): 1 patents
• H04L1/0072 ({Error control for data other than payload data, e.g. control data}): 1 patents
• H04L1/08 (by repeating transmission, e.g. Verdan system {(): 1 patents
• H04L1/1809 (Automatic repetition systems, e.g. Van Duuren systems): 1 patents
• G06F2212/7203 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F11/1471 ({involving logging of persistent data for recovery}): 1 patents
• G06F3/0634 ({by changing the state or mode of one or more devices}): 1 patents
• G06F3/0647 ({Migration mechanisms}): 1 patents
• G06F3/0685 ({Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}): 1 patents
• G11C7/20 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C14/0018 ({whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor}): 1 patents
• G06F2201/805 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2201/84 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F12/0864 (using pseudo-associative means, e.g. set-associative or hashing): 1 patents
• G06F2212/6032 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F11/0751 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0772 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0784 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/079 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/1658 ({Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit}): 1 patents
• G06F11/2007 ({using redundant communication media}): 1 patents
• G06F13/4027 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• Y02D10/00 (No explanation available): 1 patents
• G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G06F12/0851 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G06F12/1027 (using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]): 1 patents
• G11C8/06 (Address interface arrangements, e.g. address buffers): 1 patents
• G06F2212/1044 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F11/1666 ({where the redundant component is memory or memory area}): 1 patents
• G11C29/42 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/4401 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/70 ({Masking faults in memories by using spares or by reconfiguring}): 1 patents
• H03M13/1575 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• G11C2029/4402 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/765 ({using address translation or modifications}): 1 patents
• G11C11/4082 ({Address Buffers; level conversion circuits}): 1 patents
• G06F12/06 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (): 1 patents
• G06F13/1673 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G11C5/04 (Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports): 1 patents
• G11C7/1051 ({Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}): 1 patents
• G11C7/1078 ({Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}): 1 patents
• G11C11/4093 (Input/output [I/O] data interface arrangements, e.g. data buffers): 1 patents
• G11C7/22 (Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management): 1 patents
• G11C11/4076 (Timing circuits (for regeneration management): 1 patents
• G11C7/1066 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/1072 ({for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}): 1 patents

Companies

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List of Companies

• Rambus Inc.: 8 patents
• RAMBUS INC.: 1 patents

Collaborators

• Ely K. Tsern of Los Altos CA (US) (2 collaborations)
• Ely Tsern of Los Altos CA (US) (2 collaborations)
• Mark A. Horowitz of Menlo Park CA (US) (1 collaborations)
• J. James Tringali of Los Altos CA (US) (1 collaborations)
• Thomas Vogelsang of Mountain View CA (US) (1 collaborations)
• Michael Raymond Miller of Raleigh NC (US) (1 collaborations)
• Collins Williams of Raleigh NC (US) (1 collaborations)
• Kenneth L. Wright of Sunnyvale CA (US) (1 collaborations)
• Suresh Rajan of San Jose CA (US) (1 collaborations)
• Scott C. Best of Palo Alto CA (US) (1 collaborations)