Category:Kunal R. Parekh of Boise ID (US)

Kunal R. Parekh of Boise ID (US)

Executive Summary

Kunal R. Parekh of Boise ID (US) is an inventor who has filed 10 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (6 patents), {Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected} (5 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (5 patents), and they have worked with companies such as Micron Technology, Inc. (10 patents). Their most frequent collaborators include (4 collaborations), (3 collaborations), (3 collaborations).

Patent Filing Activity

File:Kunal R. Parekh of Boise ID (US) Monthly Patent Applications.png

Technology Areas

File:Kunal R. Parekh of Boise ID (US) Top Technology Areas.png

List of Technology Areas

• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 6 patents
• H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 5 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 5 patents
• H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H01L2924/1431 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 5 patents
• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 4 patents
• H01L2924/1436 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L2224/08146 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2225/06589 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• G11C11/4093 (Input/output [I/O] data interface arrangements, e.g. data buffers): 2 patents
• G06F3/0656 ({Data buffering arrangements}): 2 patents
• G06F13/1673 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
• G06F13/28 (using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (): 2 patents
• G11C7/08 (Control thereof): 2 patents
• G11C7/1039 ({using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}): 2 patents
• G11C11/4087 ({Address decoders, e.g. bit - or word line decoders; Multiple line decoders}): 2 patents
• G11C11/4091 (Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating): 2 patents
• G11C11/4096 (Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches): 2 patents
• G16B30/00 (ICT specially adapted for sequence analysis involving nucleotides or amino acids): 2 patents
• G16B50/10 (BIOINFORMATICS, i.e. INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR GENETIC OR PROTEIN-RELATED DATA PROCESSING IN COMPUTATIONAL MOLECULAR BIOLOGY): 2 patents
• H01L21/78 (with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 2 patents
• H01L22/12 ({for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions (electrical measurement of diffusions): 2 patents
• H01L24/48 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• G06F2213/28 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
• H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/0801 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/1601 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/16221 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/48091 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/48145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/48221 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06517 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06527 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2924/14335 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06544 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2924/1434 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 2 patents
• H10B43/27 (ELECTRONIC MEMORY DEVICES): 2 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06548 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06586 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
• H01L21/50 (Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups): 1 patents
• H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/76877 ({Thin films associated with contacts of capacitors}): 1 patents
• H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L27/0688 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49894 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L24/96 ({the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting}): 1 patents
• H01L24/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/96 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B41/27 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B41/35 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B43/35 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L21/304 (Mechanical treatment, e.g. grinding, polishing, cutting {(): 1 patents
• H01L21/6835 ({using temporarily an auxiliary support}): 1 patents
• H01L24/89 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/544 (Marks applied to semiconductor devices {or parts}, e.g. registration marks, {alignment structures, wafer maps (test patterns for characterising or monitoring manufacturing processes): 1 patents
• H01L2221/68368 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2223/5446 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05647 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/89 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10D30/025 (No explanation available): 1 patents
• H10D30/63 (No explanation available): 1 patents
• H10D48/36 (No explanation available): 1 patents

Companies

File:Kunal R. Parekh of Boise ID (US) Top Companies.png

List of Companies

• Micron Technology, Inc.: 10 patents

Collaborators

• Wei Zhou of Boise ID (US) (4 collaborations)
• Akshay N. Singh of Boise ID (US) (3 collaborations)
• Bharat Bhushan (3 collaborations)
• Aliasger T. Zaidy of Seattle WA (US) (2 collaborations)
• Glen E. Hush of Boise ID (US) (2 collaborations)
• Sean S. Eilert of Penryn CA (US) (2 collaborations)
• Bret K. Street of Meridian ID (US) (2 collaborations)
• Kyle K. Kirby of Eagle ID (US) (1 collaborations)
• Albert Fayrushin of Boise ID (US) (1 collaborations)
• Haitao Liu of Boise ID (US) (1 collaborations)
• Justin B. Dorhout of Boise ID (US) (1 collaborations)
• David Daycock of Boise ID (US) (1 collaborations)
• Martin C. Roberts of Boise ID (US) (1 collaborations)
• Yushi Hu of Boise ID (US) (1 collaborations)