Category:Scott E. Schaefer of Boise ID (US)

Scott E. Schaefer of Boise ID (US)

Executive Summary

Scott E. Schaefer of Boise ID (US) is an inventor who has filed 4 patents. Their primary areas of innovation include {in sector programmable memories, e.g. flash disk ( (2 patents), CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means (2 patents), {Command handling arrangements, e.g. command buffers, queues, command scheduling} (1 patents), and they have worked with companies such as Lodestar Licensing Group LLC (4 patents). Their most frequent collaborators include (4 collaborations).

Patent Filing Activity

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Technology Areas

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List of Technology Areas

G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 2 patents
H03M13/2906 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 2 patents
G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 1 patents
G06F3/0607 ({by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device}): 1 patents
G06F3/0658 ({Controller construction arrangements}): 1 patents
G06F3/0688 ({Non-volatile semiconductor memory arrays}): 1 patents
G06F9/30196 ({using decoder, e.g. decoder per instruction set, adaptable or programmable decoders}): 1 patents
G06F11/1012 ({using codes or arrangements adapted for a specific type of error (): 1 patents
G06F11/073 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
G06F11/0793 ({Remedial or corrective actions (recovery from an exception in an instruction pipeline): 1 patents
G06F13/28 (using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (): 1 patents
G06F11/1076 ({Parity data used in redundant arrays of independent storages, e.g. in RAID systems}): 1 patents
G11C11/221 ({using ferroelectric capacitors}): 1 patents
G11C11/4087 ({Address decoders, e.g. bit - or word line decoders; Multiple line decoders}): 1 patents
G11C11/4091 (Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating): 1 patents