Category:Scott M. Hayes of Chandler AZ (US)

Scott M. Hayes of Chandler AZ (US)

Executive Summary

Scott M. Hayes of Chandler AZ (US) is an inventor who has filed 4 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (2 patents), and they have worked with companies such as NXP USA, Inc. (4 patents). Their most frequent collaborators include (3 collaborations), (1 collaborations), (1 collaborations).

Patent Filing Activity

File:Scott M. Hayes of Chandler AZ (US) Monthly Patent Applications.png

Technology Areas

File:Scott M. Hayes of Chandler AZ (US) Top Technology Areas.png

List of Technology Areas

• H01L24/48 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2224/48227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/3121 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/568 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/561 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/67126 ({Apparatus for sealing, encapsulating, glassing, decapsulating or the like (processes): 1 patents
• H01L22/26 ({Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement (endpoint detection arrangements in CMP apparatus): 1 patents
• H01L23/3157 ({Partial encapsulation or coating (mask layer used as insulation layer): 1 patents
• H01L24/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/56 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49833 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L24/85 ({using a wire connector (wire bonding in general): 1 patents
• H01R12/62 (connecting to rigid printed circuits or like structures): 1 patents
• H01L2224/85 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/24 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/315 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/82 ({by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] (interconnection structure between a plurality of semiconductor chips): 1 patents
• H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L25/16 (the devices being of types provided for in two or more different main groups of groups): 1 patents
• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 1 patents
• H01L23/49827 ({Via connections through the substrates, e.g. pins going through the substrate, coaxial cables (): 1 patents
• H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/19 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/211 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/24011 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/2402 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/24155 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/32227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/82101 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/82105 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/82951 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01R12/57 (surface mounting terminals): 1 patents
• H01L23/66 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01Q1/2283 ({mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package}): 1 patents
• H01Q15/14 (Reflecting surfaces; Equivalent structures {(electromagnetic shields): 1 patents
• H01L2223/6616 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2223/6677 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08235 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/48091 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/142 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/182 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

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List of Companies

• NXP USA, Inc.: 4 patents

Collaborators

• Michael B. Vincent of Chandler AZ (US) (3 collaborations)
• Zhiwei Gong of Chandler AZ (US) (1 collaborations)
• Vivek Gupta of Phoenix AZ (US) (1 collaborations)
• Richard Te Gan of Chandler AZ (US) (1 collaborations)
• Stephen Ryan Hooper of Queen Creek AZ (US) (1 collaborations)
• Dwight Lee Daniels of Phoenix AZ (US) (1 collaborations)
• Chayathorn Saklang of Mesa AZ (US) (1 collaborations)
• Michael B. Vincent of Payson AZ (US) (1 collaborations)