Category:Yu-Chung Lien of San Jose CA (US)

Yu-Chung Lien of San Jose CA (US)

Executive Summary

Yu-Chung Lien of San Jose CA (US) is an inventor who has filed 13 patents. Their primary areas of innovation include {comprising cells having several storage transistors connected in series} (5 patents), Sensing or reading circuits; Data output circuits (4 patents), Programming or data input circuits (4 patents), and they have worked with companies such as Micron Technology, Inc. (11 patents), MICRON TECHNOLOGY, INC. (2 patents). Their most frequent collaborators include (12 collaborations), (2 collaborations), (2 collaborations).

Patent Filing Activity

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Technology Areas

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List of Technology Areas

• G11C16/0483 ({comprising cells having several storage transistors connected in series}): 5 patents
• G11C16/26 (Sensing or reading circuits; Data output circuits): 4 patents
• G11C16/102 (Programming or data input circuits): 4 patents
• G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 3 patents
• G11C16/32 (Timing circuits): 3 patents
• G11C16/08 (Address circuits; Decoders; Word-line control circuits): 3 patents
• G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 3 patents
• G11C16/349 ({Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}): 3 patents
• G11C29/52 (STATIC STORES (semiconductor memory devices): 2 patents
• G06F3/0673 ({Single storage device}): 2 patents
• G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 2 patents
• G11C16/10 (Programming or data input circuits): 2 patents
• G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 2 patents
• G01R19/165 (Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values): 1 patents
• G06F3/064 ({Management of blocks}): 1 patents
• G06F11/073 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0769 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G11C29/08 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/50004 (STATIC STORES (semiconductor memory devices): 1 patents
• G06F3/0644 ({Management of space entities, e.g. partitions, extents, pools}): 1 patents
• G11C16/12 (Programming voltage switching circuits): 1 patents
• G06F3/0616 ({in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}): 1 patents
• G06F3/0653 ({Monitoring storage devices or systems}): 1 patents
• G11C11/5642 ({Sensing or reading circuits; Data output circuits}): 1 patents
• G11C16/24 (Bit-line control circuits): 1 patents
• G11C16/3431 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C16/3404 ({Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}): 1 patents
• G11C16/3418 (STATIC STORES (semiconductor memory devices): 1 patents

Companies

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List of Companies

• Micron Technology, Inc.: 11 patents
• MICRON TECHNOLOGY, INC.: 2 patents

Collaborators

• Zhenming Zhou of San Jose CA (US) (12 collaborations)
• Jun Wan of San Jose CA (US) (2 collaborations)
• Tomer Tzvi Eliash of Sunnyvale CA (US) (2 collaborations)
• Daniel Zhang of Milpitas CA (US) (1 collaborations)
• Peng Zhang of Los Altos CA (US) (1 collaborations)
• Murong Lang of San Jose CA (US) (1 collaborations)
• Shyam Sunder Raghunathan (1 collaborations)
• Tingjun Xie of Milpitas CA (US) (1 collaborations)
• Aaron Lee of Sunnyvale CA (US) (1 collaborations)
• Huai-Yuan Tseng of San Ramon CA (US) (1 collaborations)
• John Paul Aglubat of Meridian ID (US) (1 collaborations)
• Ching-Huang Lu of Fremont CA (US) (1 collaborations)
• Ting Luo of Santa Clara CA (US) (1 collaborations)