Category:Hiroshi MAEJIMA: Difference between revisions

Latest revision as of 01:14, 30 March 2025

Hiroshi MAEJIMA

Executive Summary

Hiroshi MAEJIMA is an inventor who has filed 3 patents. Their primary areas of innovation include STATIC STORES (semiconductor memory devices (2 patents), {comprising cells having several storage transistors connected in series} (2 patents), Programming or data input circuits (1 patents), and they have worked with companies such as Kioxia Corporation (3 patents). Their most frequent collaborators include (1 collaborations).

Patent Filing Activity

File:Hiroshi MAEJIMA Monthly Patent Applications.png

Technology Areas

File:Hiroshi MAEJIMA Top Technology Areas.png

List of Technology Areas

G11C5/063 (STATIC STORES (semiconductor memory devices): 2 patents
G11C16/0483 ({comprising cells having several storage transistors connected in series}): 2 patents
G11C16/10 (Programming or data input circuits): 1 patents
G11C5/02 (STATIC STORES (semiconductor memory devices): 1 patents
G11C16/04 (STATIC STORES (semiconductor memory devices): 1 patents
G11C16/08 (Address circuits; Decoders; Word-line control circuits): 1 patents
G11C16/3418 (STATIC STORES (semiconductor memory devices): 1 patents
G11C16/3422 (STATIC STORES (semiconductor memory devices): 1 patents
G11C7/1039 ({using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}): 1 patents
G11C7/08 (Control thereof): 1 patents
G11C7/1063 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
G11C7/109 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
G11C16/16 (STATIC STORES (semiconductor memory devices): 1 patents
G11C16/26 (Sensing or reading circuits; Data output circuits): 1 patents
H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 1 patents
H10B41/10 (ELECTRONIC MEMORY DEVICES): 1 patents
H10B41/35 (ELECTRONIC MEMORY DEVICES): 1 patents
H10B43/10 (ELECTRONIC MEMORY DEVICES): 1 patents
H10B43/35 (ELECTRONIC MEMORY DEVICES): 1 patents

Companies

File:Hiroshi MAEJIMA Top Companies.png

List of Companies

Kioxia Corporation: 3 patents

Collaborators

Toshifumi HASHIMOTO (1 collaborations)

Subcategories

This category has the following 2 subcategories, out of 2 total.

H

► Hiroshi MAEJIMA‎ (2 C)

T

► Tomoya SANUKI‎ (2 C)

@@ Line 2: / Line 2: @@
 === Executive Summary ===
-Hiroshi MAEJIMA is an inventor who has filed 10 patents. Their primary areas of innovation include {comprising cells having several storage transistors connected in series} (8 patents), Address circuits; Decoders; Word-line control circuits (7 patents), Sensing or reading circuits; Data output circuits (7 patents), and they have worked with companies such as Kioxia Corporation (9 patents), KIOXIA CORPORATION (1 patents). Their most frequent collaborators include [[Category:Tomoya SANUKI|Tomoya SANUKI]] (1 collaborations), [[Category:Tetsuaki UTSUMI|Tetsuaki UTSUMI]] (1 collaborations), [[Category:Katsuaki ISOBE|Katsuaki ISOBE]] (1 collaborations).
+Hiroshi MAEJIMA is an inventor who has filed 3 patents. Their primary areas of innovation include STATIC STORES  (semiconductor memory devices (2 patents), {comprising cells having several storage transistors connected in series} (2 patents), Programming or data input circuits (1 patents), and they have worked with companies such as Kioxia Corporation (3 patents). Their most frequent collaborators include [[Category:Toshifumi HASHIMOTO|Toshifumi HASHIMOTO]] (1 collaborations).
 === Patent Filing Activity ===
@@ Line 11: / Line 11: @@
 ==== List of Technology Areas ====
-* [[:Category:CPC_G11C16/0483|G11C16/0483]] ({comprising cells having several storage transistors connected in series}): 8 patents
+* [[:Category:CPC_G11C5/063|G11C5/063]] (STATIC STORES  (semiconductor memory devices): 2 patents
-* [[:Category:CPC_G11C16/08|G11C16/08]] (Address circuits; Decoders; Word-line control circuits): 7 patents
+* [[:Category:CPC_G11C16/0483|G11C16/0483]] ({comprising cells having several storage transistors connected in series}): 2 patents
-* [[:Category:CPC_G11C16/26|G11C16/26]] (Sensing or reading circuits; Data output circuits): 7 patents
+* [[:Category:CPC_G11C16/10|G11C16/10]] (Programming or data input circuits): 1 patents
-* [[:Category:CPC_G11C16/10|G11C16/10]] (Programming or data input circuits): 4 patents
+* [[:Category:CPC_G11C5/02|G11C5/02]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_H01L24/08|H01L24/08]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
+* [[:Category:CPC_G11C16/04|G11C16/04]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_H01L25/0657|H01L25/0657]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
+* [[:Category:CPC_G11C16/08|G11C16/08]] (Address circuits; Decoders; Word-line control circuits): 1 patents
-* [[:Category:CPC_H01L25/18|H01L25/18]] (the devices being of types provided for in two or more different subgroups of the same main group of groups): 3 patents
+* [[:Category:CPC_G11C16/3418|G11C16/3418]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_H01L2224/08145|H01L2224/08145]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
+* [[:Category:CPC_G11C16/3422|G11C16/3422]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_H01L2924/1431|H01L2924/1431]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
+* [[:Category:CPC_G11C7/1039|G11C7/1039]] ({using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}): 1 patents
-* [[:Category:CPC_H01L2924/14511|H01L2924/14511]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
+* [[:Category:CPC_G11C7/08|G11C7/08]] (Control thereof): 1 patents
-* [[:Category:CPC_G11C5/063|G11C5/063]] (STATIC STORES  (semiconductor memory devices): 3 patents
+* [[:Category:CPC_G11C7/1063|G11C7/1063]] (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
-* [[:Category:CPC_G11C16/16|G11C16/16]] (STATIC STORES  (semiconductor memory devices): 2 patents
+* [[:Category:CPC_G11C7/109|G11C7/109]] (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
-* [[:Category:CPC_H10B80/00|H10B80/00]] (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 2 patents
+* [[:Category:CPC_G11C16/16|G11C16/16]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_G11C7/06|G11C7/06]] (Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}): 2 patents
+* [[:Category:CPC_G11C16/26|G11C16/26]] (Sensing or reading circuits; Data output circuits): 1 patents
-* [[:Category:CPC_G11C16/3418|G11C16/3418]] (STATIC STORES  (semiconductor memory devices): 2 patents
+* [[:Category:CPC_H01L23/5283|H01L23/5283]] ({Geometry or} layout of the interconnection structure {(): 1 patents
-* [[:Category:CPC_G11C16/3427|G11C16/3427]] (STATIC STORES  (semiconductor memory devices): 2 patents
+* [[:Category:CPC_H10B41/10|H10B41/10]] (ELECTRONIC MEMORY DEVICES): 1 patents
-* [[:Category:CPC_H01L23/5226|H01L23/5226]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
+* [[:Category:CPC_H10B41/35|H10B41/35]] (ELECTRONIC MEMORY DEVICES): 1 patents
-* [[:Category:CPC_H01L23/528|H01L23/528]] ({Geometry or} layout of the interconnection structure {(): 1 patents
 * [[:Category:CPC_H10B43/10|H10B43/10]] (ELECTRONIC MEMORY DEVICES): 1 patents
-* [[:Category:CPC_H10B43/27|H10B43/27]] (ELECTRONIC MEMORY DEVICES): 1 patents
 * [[:Category:CPC_H10B43/35|H10B43/35]] (ELECTRONIC MEMORY DEVICES): 1 patents
-* [[:Category:CPC_H10B43/40|H10B43/40]] (ELECTRONIC MEMORY DEVICES): 1 patents
-* [[:Category:CPC_G11C16/3459|G11C16/3459]] ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 1 patents
-* [[:Category:CPC_H01L2225/06524|H01L2225/06524]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2225/06593|H01L2225/06593]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_H01L2225/06596|H01L2225/06596]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
-* [[:Category:CPC_G11C5/02|G11C5/02]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_G11C16/3422|G11C16/3422]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_G11C16/04|G11C16/04]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_G06F3/0614|G06F3/0614]] ({Improving the reliability of storage systems}): 1 patents
-* [[:Category:CPC_G06F3/0631|G06F3/0631]] ({by allocating resources to storage systems}): 1 patents
-* [[:Category:CPC_G06F3/0652|G06F3/0652]] ({Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}): 1 patents
-* [[:Category:CPC_G06F3/0659|G06F3/0659]] ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 1 patents
-* [[:Category:CPC_G06F3/0665|G06F3/0665]] ({at area level, e.g. provisioning of virtual or logical volumes}): 1 patents
-* [[:Category:CPC_G06F3/0679|G06F3/0679]] ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 1 patents
-* [[:Category:CPC_G06F12/0246|G06F12/0246]] ({in block erasable memory, e.g. flash memory}): 1 patents
-* [[:Category:CPC_G11C11/5635|G11C11/5635]] ({Erasing circuits}): 1 patents
-* [[:Category:CPC_G06F2212/1032|G06F2212/1032]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
-* [[:Category:CPC_G06F2212/152|G06F2212/152]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
-* [[:Category:CPC_G06F2212/214|G06F2212/214]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
-* [[:Category:CPC_G06F2212/7202|G06F2212/7202]] (ELECTRIC DIGITAL DATA PROCESSING  (computer systems based on specific computational models): 1 patents
-* [[:Category:CPC_G11C2213/71|G11C2213/71]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_G11C16/14|G11C16/14]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_G11C16/24|G11C16/24]] (Bit-line control circuits): 1 patents
-* [[:Category:CPC_G11C16/28|G11C16/28]] (STATIC STORES  (semiconductor memory devices): 1 patents
-* [[:Category:CPC_G11C16/32|G11C16/32]] (Timing circuits): 1 patents
 === Companies ===
@@ Line 62: / Line 35: @@
 ==== List of Companies ====
-* Kioxia Corporation: 9 patents
+* Kioxia Corporation: 3 patents
-* KIOXIA CORPORATION: 1 patents
 === Collaborators ===
-* [[:Category:Tomoya SANUKI|Tomoya SANUKI]][[Category:Tomoya SANUKI]] (1 collaborations)
+* [[:Category:Toshifumi HASHIMOTO|Toshifumi HASHIMOTO]][[Category:Toshifumi HASHIMOTO]] (1 collaborations)
-* [[:Category:Tetsuaki UTSUMI|Tetsuaki UTSUMI]][[Category:Tetsuaki UTSUMI]] (1 collaborations)
-* [[:Category:Katsuaki ISOBE|Katsuaki ISOBE]][[Category:Katsuaki ISOBE]] (1 collaborations)
-* [[:Category:Keita KIMURA|Keita KIMURA]][[Category:Keita KIMURA]] (1 collaborations)
 [[Category:Hiroshi MAEJIMA]]
 [[Category:Inventors]]
 [[Category:Inventors filing patents with Kioxia Corporation]]
-[[Category:Inventors filing patents with KIOXIA CORPORATION]]