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Category:Chih-Liang CHEN - WikiTrademarks Jump to content

Category:Chih-Liang CHEN

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Chih-Liang CHEN

Executive Summary

Chih-Liang CHEN is an inventor who has filed 14 patents. Their primary areas of innovation include Floor-planning or layout, e.g. partitioning or placement (5 patents), Circuit design at the physical level (physical level design for reconfigurable circuits (4 patents), Circuit design at the physical level (physical level design for reconfigurable circuits (4 patents), and they have worked with companies such as TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (13 patents), Taiwan Semiconductor Manufacturing Company, Ltd. (1 patents). Their most frequent collaborators include (6 collaborations), (5 collaborations), (5 collaborations).

Patent Filing Activity

File:Chih-Liang CHEN Monthly Patent Applications.png

Technology Areas

File:Chih-Liang CHEN Top Technology Areas.png

List of Technology Areas

  • G06F30/392 (Floor-planning or layout, e.g. partitioning or placement): 5 patents
  • G06F30/398 (Circuit design at the physical level (physical level design for reconfigurable circuits): 4 patents
  • G06F30/394 (Circuit design at the physical level (physical level design for reconfigurable circuits): 4 patents
  • H01L27/0207 ({Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique}): 4 patents
  • H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 4 patents
  • H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
  • H01L21/76898 ({formed through a semiconductor substrate}): 3 patents
  • H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 3 patents
  • H01L21/823475 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 3 patents
  • H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L21/823871 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 3 patents
  • G06F30/39 (Circuit design at the physical level (physical level design for reconfigurable circuits): 2 patents
  • H01L29/0665 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 2 patents
  • H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/585 ({comprising conductive layers or plates or strips or rods or rings (): 1 patents
  • H01L21/765 (Making of isolation regions between components): 1 patents
  • H01L21/76885 ({By forming conductive members before deposition of protective insulating material, e.g. pillars, studs}): 1 patents
  • H01L27/0255 ({using diodes as protective elements}): 1 patents
  • H01Q9/0407 ({Substantially flat resonant element parallel to ground plane, e.g. patch antenna (dipole): 1 patents
  • H01L27/11807 (Masterslice integrated circuits): 1 patents
  • H01L2027/11875 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L27/088 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/0669 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L27/0694 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/41733 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/0259 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/8221 ({Three dimensional integrated circuits stacked in different levels}): 1 patents
  • H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L29/66742 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/0696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors): 1 patents
  • G06F2119/12 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
  • H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/823821 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L21/823828 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L21/823864 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L27/0924 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 1 patents
  • H01L29/66795 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/785 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2029/7858 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • G06F2111/20 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
  • H01L21/82385 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
  • H01L29/42376 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

File:Chih-Liang CHEN Top Companies.png

List of Companies

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 13 patents
  • Taiwan Semiconductor Manufacturing Company, Ltd.: 1 patents

Collaborators

Subcategories

This category has the following 3 subcategories, out of 3 total.

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