Category:Zhenming Zhou of San Jose CA (US)

Zhenming Zhou of San Jose CA (US)

Executive Summary

Zhenming Zhou of San Jose CA (US) is an inventor who has filed 45 patents. Their primary areas of innovation include {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} (16 patents), Sensing or reading circuits; Data output circuits (10 patents), {Circuits or methods to verify correct programming of nonvolatile memory cells} (9 patents), and they have worked with companies such as Micron Technology, Inc. (37 patents), MICRON TECHNOLOGY, INC. (8 patents). Their most frequent collaborators include (25 collaborations), (20 collaborations), (7 collaborations).

Patent Filing Activity

File:Zhenming Zhou of San Jose CA (US) Monthly Patent Applications.png

Technology Areas

File:Zhenming Zhou of San Jose CA (US) Top Technology Areas.png

List of Technology Areas

• G06F3/0679 ({Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}): 16 patents
• G11C16/26 (Sensing or reading circuits; Data output circuits): 10 patents
• G11C16/3459 ({Circuits or methods to verify correct programming of nonvolatile memory cells}): 9 patents
• G11C16/102 (Programming or data input circuits): 8 patents
• G11C16/08 (Address circuits; Decoders; Word-line control circuits): 8 patents
• G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 6 patents
• G06F3/0655 ({Replication mechanisms}): 6 patents
• G11C16/10 (Programming or data input circuits): 6 patents
• G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 5 patents
• G11C16/3404 ({Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells}): 4 patents
• G11C16/0483 ({comprising cells having several storage transistors connected in series}): 4 patents
• G11C29/52 (STATIC STORES (semiconductor memory devices): 4 patents
• G06F3/0629 ({Configuration or reconfiguration of storage systems}): 3 patents
• G06F3/0644 ({Management of space entities, e.g. partitions, extents, pools}): 3 patents
• G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 3 patents
• G06F3/0653 ({Monitoring storage devices or systems}): 3 patents
• G11C16/349 ({Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}): 3 patents
• G06F3/064 ({Management of blocks}): 2 patents
• G11C16/3495 ({Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}): 2 patents
• G11C16/30 (Power supply circuits): 2 patents
• G11C29/022 (STATIC STORES (semiconductor memory devices): 2 patents
• G11C16/24 (Bit-line control circuits): 2 patents
• G06F3/0611 ({in relation to response time}): 2 patents
• G06F3/0616 ({in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}): 2 patents
• G11C16/28 (STATIC STORES (semiconductor memory devices): 2 patents
• G11C16/16 (STATIC STORES (semiconductor memory devices): 2 patents
• G06F12/1009 (Address translation): 1 patents
• G11C7/1063 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C5/063 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/50004 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/783 ({with refresh of replacement cells, e.g. in DRAMs}): 1 patents
• G11C16/32 (Timing circuits): 1 patents
• G11C16/12 (Programming voltage switching circuits): 1 patents
• G06F3/0652 ({Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket}): 1 patents
• G11C16/3445 ({Circuits or methods to verify correct erasure of nonvolatile memory cells}): 1 patents
• G06F3/061 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
• G11C11/5628 ({Programming or writing circuits; Data input circuits}): 1 patents
• G11C11/5671 ({using charge trapping in an insulator}): 1 patents
• G11C16/3431 (STATIC STORES (semiconductor memory devices): 1 patents
• G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 1 patents
• G06F11/1489 ({through recovery blocks}): 1 patents
• G06F11/3409 ({for performance assessment}): 1 patents
• G11C16/3418 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C11/40618 (STATIC STORES (semiconductor memory devices): 1 patents
• G06N20/00 (Machine learning): 1 patents
• G11C11/4096 (Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches): 1 patents
• G11C11/4074 (Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits): 1 patents
• G11C11/4076 (Timing circuits (for regeneration management): 1 patents

Companies

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List of Companies

• Micron Technology, Inc.: 37 patents
• MICRON TECHNOLOGY, INC.: 8 patents

Collaborators

• Yu-Chung Lien of San Jose CA (US) (25 collaborations)
• Murong Lang of San Jose CA (US) (20 collaborations)
• Ching-Huang Lu of Fremont CA (US) (7 collaborations)
• Li-Te Chang of San Jose CA (US) (5 collaborations)
• Tingjun Xie of Milpitas CA (US) (4 collaborations)
• Christina Papagianni of San Jose CA (US) (4 collaborations)
• Zhongguang Xu of San Jose CA (US) (4 collaborations)
• Jian Huang of Union City CA (US) (4 collaborations)
• Jiangli Zhu of San Jose CA (US) (3 collaborations)
• Peng Zhang of Los Altos CA (US) (3 collaborations)
• Jun Wan of San Jose CA (US) (3 collaborations)
• Nagendra Prasad Ganesh Rao of Folsom CA (US) (3 collaborations)
• Ting Luo of Santa Clara CA (US) (2 collaborations)
• Ronit Roneel Prakash (2 collaborations)
• Tomer Tzvi Eliash of Sunnyvale CA (US) (1 collaborations)
• Fangfang Zhu of San Jose CA (US) (1 collaborations)
• Lei Lin of Fremont CA (US) (1 collaborations)
• Pitamber Shukla of San Jose CA (US) (1 collaborations)
• Zhengang Chen of San Jose CA (US) (1 collaborations)
• Vivek Shivhare of Milpitas CA (US) (1 collaborations)
• Vinh Diep of Hayward CA (US) (1 collaborations)
• Aaron Lee of Sunnyvale CA (US) (1 collaborations)
• Pitamber Shukla of Boise ID (US) (1 collaborations)
• Sead Zildzic of Folsom CA (US) (1 collaborations)
• Joshua Garrison of Folsom CA (US) (1 collaborations)
• Charles Kwong of Redwood City CA (US) (1 collaborations)
• Wei Wang of Fremont CA (US) (1 collaborations)
• Michael G. Miller of Boise ID (US) (1 collaborations)
• Ankit V. Vashi of San Jose CA (US) (1 collaborations)
• Jung Sheng Hoei of Newark CA (US) (1 collaborations)
• Paing Z. Htet of Union City CA (US) (1 collaborations)
• Sead Zildzic, JR. of Folsom CA (US) (1 collaborations)
• Thomas Fiala of Folsom CA (US) (1 collaborations)
• Li-Te Chang of Boise ID (US) (1 collaborations)
• Charles See Yeung Kwong of Redwood City CA (US) (1 collaborations)
• Vamsi Pavan Rayaprolu of Santa Clara CA (US) (1 collaborations)
• Seungjune Jeon of Santa Clara CA (US) (1 collaborations)