Category:Navneet K. Jain of Milpitas CA (US)

Navneet K. Jain of Milpitas CA (US)

Executive Summary

Navneet K. Jain of Milpitas CA (US) is an inventor who has filed 7 patents. Their primary areas of innovation include {Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique} (2 patents), STATIC STORES (semiconductor memory devices (1 patents), {Word-line or row circuits} (1 patents), and they have worked with companies such as GlobalFoundries U.S. Inc. (7 patents). Their most frequent collaborators include (3 collaborations), (2 collaborations), (2 collaborations).

Patent Filing Activity

File:Navneet K. Jain of Milpitas CA (US) Monthly Patent Applications.png

Technology Areas

File:Navneet K. Jain of Milpitas CA (US) Top Technology Areas.png

List of Technology Areas

• H01L27/0207 ({Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique}): 2 patents
• G11C5/063 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C13/0028 ({Word-line or row circuits}): 1 patents
• G11C13/0069 ({Writing or programming circuits or methods}): 1 patents
• G11C11/22 (using ferroelectric elements): 1 patents
• G11C5/147 ({Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (): 1 patents
• G01R19/16519 (Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values): 1 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76224 ({using trench refilling with dielectric materials (trench filling with polycristalline silicon): 1 patents
• H01L21/823878 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
• G05F3/262 (SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES (regulating the timing or recurrence frequency of pulses in radar or radio navigation systems): 1 patents
• H01L29/78391 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/792 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/7851 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/28123 ({Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects}): 1 patents
• H01L29/1037 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/4983 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 1 patents
• H01L29/66795 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H03K3/012 (PULSE TECHNIQUE (measuring pulse characteristics): 1 patents
• H03K3/037 (PULSE TECHNIQUE (measuring pulse characteristics): 1 patents
• H03K5/01 (Shaping pulses (discrimination against noise or interference): 1 patents
• H03K2005/00013 (PULSE TECHNIQUE (measuring pulse characteristics): 1 patents

Companies

File:Navneet K. Jain of Milpitas CA (US) Top Companies.png

List of Companies

• GlobalFoundries U.S. Inc.: 7 patents

Collaborators

• James P. Mazza of Saratoga Springs NY (US) (3 collaborations)
• Venkatesh P. Gopinath of Fremont CA (US) (2 collaborations)
• David Charles Pritchard of Schenectady NY (US) (2 collaborations)
• Hong Yu of Clifton Park NY (US) (2 collaborations)
• Mahbub Rashed of Cupertino CA (US) (2 collaborations)
• Sven Beyer (1 collaborations)
• Dzung T. Tran of Austin TX (US) (1 collaborations)
• Romain H.A. Feuillette of Williston VT (US) (1 collaborations)
• Jia Zeng of Sunnyvale CA (US) (1 collaborations)
• Xuelian Zhu of Sunnyvale CA (US) (1 collaborations)
• Jacob Mazza of Highland NY (US) (1 collaborations)