Category:Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US)

Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US)

Executive Summary

Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) is an inventor who has filed 13 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (11 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (6 patents), {Multilayer substrates (multilayer metallisation on monolayer substrate (6 patents), and they have worked with companies such as Intel Corporation (13 patents). Their most frequent collaborators include (11 collaborations), (8 collaborations), (2 collaborations).

Patent Filing Activity

File:Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) Monthly Patent Applications.png

Technology Areas

File:Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) Top Technology Areas.png

List of Technology Areas

• H01L23/15 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 11 patents
• H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 6 patents
• H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 6 patents
• H01L23/49827 ({Via connections through the substrates, e.g. pins going through the substrate, coaxial cables (): 5 patents
• H01L23/49838 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 5 patents
• H01L23/49894 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 4 patents
• H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/5385 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 2 patents
• H01L23/3128 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/17 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/1703 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/645 ({Inductive arrangements (): 2 patents
• H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/73 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 2 patents
• H01L2224/73204 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/24 (solid or gel at the normal operating temperature of the device {(): 1 patents
• H01L23/3675 (Cooling facilitated by shape of device {(): 1 patents
• H01L23/373 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5383 ({Multilayer substrates (): 1 patents
• H01L24/24 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/24226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L28/40 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49866 ({characterised by the materials (materials of the substrates): 1 patents
• H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
• H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L23/642 ({Capacitive arrangements (): 1 patents
• H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L23/535 (including internal interconnections, e.g. cross-under constructions {(internal lead connections): 1 patents
• H01L25/117 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/32157 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/32165 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1205 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/03 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0345 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/03452 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0347 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05022 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05073 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05558 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05571 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05573 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05644 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05664 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/13 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/6835 ({using temporarily an auxiliary support}): 1 patents
• H01L21/76843 ({formed in openings in a dielectric}): 1 patents
• H01L23/5381 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L24/14 ({of a plurality of bump connectors}): 1 patents
• H01L2224/1403 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16257 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/32225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1431 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1436 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H05K1/181 (Printed circuits structurally associated with non-printed electric components ({): 1 patents
• H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 1 patents

Companies

File:Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) Top Companies.png

List of Companies

• Intel Corporation: 13 patents

Collaborators

• Gang Duan of Chandler AZ (US) (11 collaborations)
• Minglu Liu of Chandler AZ (US) (8 collaborations)
• Jeremy Ecton of Gilbert AZ (US) (2 collaborations)
• Brandon Christian Marin of Gilbert AZ (US) (2 collaborations)
• Ibrahim El Khatib of Chandler AZ (US) (1 collaborations)
• Jesse Cole Jones of Chandler AZ (US) (1 collaborations)
• Yi Li of Chandler AZ (US) (1 collaborations)
• Robin Shea McRee of Chandler AZ (US) (1 collaborations)
• Praveen Sreeramagiri of Gilbert AZ (US) (1 collaborations)
• Marcel Arlan Wall of Phoenix AZ (US) (1 collaborations)
• Hamid Azimi of Chandler AZ (US) (1 collaborations)
• Rahul N. Manepalli of Chandler AZ (US) (1 collaborations)
• Darko Grujicic of Chandler AZ (US) (1 collaborations)
• Steve Cho of Chandler AZ (US) (1 collaborations)
• Thomas L. Sounart of Chandler AZ (US) (1 collaborations)
• Jung Kyu Han of Chandler AZ (US) (1 collaborations)
• Suddhasattwa Nad of Chandler AZ (US) (1 collaborations)
• Benjamin Duong of Phoenix AZ (US) (1 collaborations)
• Shayan Kaviani of Phoenix AZ (US) (1 collaborations)
• Hiroki Tanaka of Gilbert AZ (US) (1 collaborations)
• Haobo Chen of Chandler AZ (US) (1 collaborations)
• Jason Gamba of Gilbert AZ (US) (1 collaborations)
• Bohan Shan of Chandler AZ (US) (1 collaborations)
• Robert May of Chandler AZ (US) (1 collaborations)
• Benjamin Taylor Duong of Phoenix AZ (US) (1 collaborations)
• Bai Nie of Chandler AZ (US) (1 collaborations)
• Whitney Bryks of Tempe AZ (US) (1 collaborations)
• Tarek Adly Ibrahim of Mesa AZ (US) (1 collaborations)
• Ravindra Vijay Tanikella of Chandler AZ (US) (1 collaborations)
• Rahul Nagaraj Manepalli of Chandler AZ (US) (1 collaborations)
• Sashi Shekhar Kandanur of Phoenix AZ (US) (1 collaborations)