Category:Haitao Liu of Boise ID (US): Difference between revisions

Haitao Liu of Boise ID (US)

Executive Summary

Haitao Liu of Boise ID (US) is an inventor who has filed 19 patents. Their primary areas of innovation include STATIC STORES (semiconductor memory devices (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), ELECTRONIC MEMORY DEVICES (4 patents), and they have worked with companies such as Micron Technology, Inc. (19 patents). Their most frequent collaborators include (16 collaborations), (11 collaborations), (7 collaborations).

Patent Filing Activity

File:Haitao Liu of Boise ID (US) Monthly Patent Applications.png

Technology Areas

File:Haitao Liu of Boise ID (US) Top Technology Areas.png

List of Technology Areas

• G11C5/063 (STATIC STORES (semiconductor memory devices): 4 patents
• H01L29/24 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H10B12/05 (ELECTRONIC MEMORY DEVICES): 4 patents
• H01L29/7869 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/78642 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H10B43/27 (ELECTRONIC MEMORY DEVICES): 3 patents
• H10B41/27 (ELECTRONIC MEMORY DEVICES): 3 patents
• H01L27/1225 (the substrate being other than a semiconductor body, e.g. an insulating body): 3 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/66666 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/7827 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H10B12/20 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B12/01 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B12/00 (Dynamic random access memory [DRAM] devices): 2 patents
• G11C11/405 (with three charge-transfer gates, e.g. MOS transistors, per cell): 2 patents
• G11C11/4096 (Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches): 2 patents
• H10B12/31 (ELECTRONIC MEMORY DEVICES): 2 patents
• H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H10B41/35 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B43/35 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B99/00 (ELECTRONIC MEMORY DEVICES): 2 patents
• H01L27/124 (the substrate being other than a semiconductor body, e.g. an insulating body): 2 patents
• H10B63/34 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10N70/883 (No explanation available): 2 patents
• H01L29/66969 ({of devices having semiconductor bodies not comprising group 14 or group 13/15 materials (comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide): 2 patents
• H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L21/823885 ({with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface (with a current flow parallel to the substrate surface): 1 patents
• H01L29/78 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B10/12 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B43/50 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L29/1062 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/42396 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/0847 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B12/488 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B12/03 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B12/482 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L21/76816 ({Aspects relating to the layout of the pattern or to the size of vias or trenches (layout of the interconnections per se): 1 patents
• H01L21/76877 ({Thin films associated with contacts of capacitors}): 1 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L27/1251 (the substrate being other than a semiconductor body, e.g. an insulating body): 1 patents
• H01L29/78672 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/7881 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B41/60 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L27/10805 (including a plurality of individual components in a repetitive configuration): 1 patents
• H01L27/10873 (including a plurality of individual components in a repetitive configuration): 1 patents
• H01L27/10826 (including a plurality of individual components in a repetitive configuration): 1 patents
• G11C11/221 ({using ferroelectric capacitors}): 1 patents
• H01L27/10882 (including a plurality of individual components in a repetitive configuration): 1 patents
• G11C5/025 ({Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits,): 1 patents
• G11C5/06 (STATIC STORES (semiconductor memory devices): 1 patents
• H10B63/84 (ELECTRONIC MEMORY DEVICES): 1 patents
• G11C5/12 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C13/0002 ({using resistive RAM [RRAM] elements}): 1 patents
• H01L21/823487 ({with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface (with a current flow parallel to the substrate surface): 1 patents
• H01L29/4908 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66795 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B63/22 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B63/24 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10N70/011 (No explanation available): 1 patents
• H10N70/245 (No explanation available): 1 patents
• H10N70/828 (No explanation available): 1 patents
• H10N70/841 (No explanation available): 1 patents
• G11C11/401 (forming cells needing refreshing or charge regeneration, i.e. dynamic cells): 1 patents
• G11C2213/79 (STATIC STORES (semiconductor memory devices): 1 patents
• H01L29/78615 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B12/315 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B63/10 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B63/845 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L27/1207 ({combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits}): 1 patents
• H01L27/1255 (the substrate being other than a semiconductor body, e.g. an insulating body): 1 patents
• H01L27/1259 (the substrate being other than a semiconductor body, e.g. an insulating body): 1 patents
• H01L29/267 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• G11C11/409 (STATIC STORES (semiconductor memory devices): 1 patents
• H01L29/42384 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B12/30 (ELECTRONIC MEMORY DEVICES): 1 patents
• H10B12/50 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 1 patents

Companies

File:Haitao Liu of Boise ID (US) Top Companies.png

List of Companies

• Micron Technology, Inc.: 19 patents

Collaborators

• Kamal M. Karda of Boise ID (US) (16 collaborations)
• Durai Vishak Nirmal Ramaswamy of Boise ID (US) (11 collaborations)
• Karthik Sarpatwari of Boise ID (US) (7 collaborations)
• Si-Woo Lee of Boise ID (US) (5 collaborations)
• Scott E. Sills of Boise ID (US) (3 collaborations)
• Michael A. Smith of Boise ID (US) (1 collaborations)
• Vladimir Mikhalev of Boise ID (US) (1 collaborations)
• Eric S. Carman of San Francisco CA (US) (1 collaborations)
• Richard E. Fackenthal of Carmichael CA (US) (1 collaborations)
• Lifang Xu of Boise ID (US) (1 collaborations)
• Indra V. Chary of Boise ID (US) (1 collaborations)
• Justin B. Dorhout of Boise ID (US) (1 collaborations)
• Jian Li of Boise ID (US) (1 collaborations)
• Paolo Tessariol (1 collaborations)
• Luan C. Tran of Meridian ID (US) (1 collaborations)
• Guangyu Huang of Boise ID (US) (1 collaborations)
• Litao Yang of Boise ID (US) (1 collaborations)
• Yunfei Gao of Boise ID (US) (1 collaborations)
• Sanh D. Tang of Meridian ID (US) (1 collaborations)
• Deepak Chandra Pandey (1 collaborations)
• Anthony J. Kanago of Boise ID (US) (1 collaborations)
• Soichi Sugiura of Bristow VA (US) (1 collaborations)
• Chandra Mouli of Boise ID (US) (1 collaborations)
• Yi Fang Lee of Boise ID (US) (1 collaborations)
• Ramanathan Gandhi of Boise ID (US) (1 collaborations)
• Sameer Chhajed of Boise ID (US) (1 collaborations)
• Kirk D. Prall of Boise ID (US) (1 collaborations)