Category:Belgacem Haba of Saratoga CA (US)

Belgacem Haba of Saratoga CA (US)

Executive Summary

Belgacem Haba of Saratoga CA (US) is an inventor who has filed 9 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (6 patents), {Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected} (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (6 patents), Adeia Semiconductor Bonding Technologies Inc. (3 patents). Their most frequent collaborators include (6 collaborations), (2 collaborations), (1 collaborations).

Patent Filing Activity

File:Belgacem Haba of Saratoga CA (US) Monthly Patent Applications.png

Technology Areas

File:Belgacem Haba of Saratoga CA (US) Top Technology Areas.png

List of Technology Areas

H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 6 patents
H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 4 patents
H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
H01L2224/08238 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
H01L2924/351 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
H01L2224/08225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
H01L23/5223 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 1 patents
H01L24/02 ({Bonding areas (on insulating substrates, e.g. chip carriers,): 1 patents
H01L24/06 ({of a plurality of bonding areas}): 1 patents
H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L25/16 (the devices being of types provided for in two or more different main groups of groups): 1 patents
H01L29/945 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/02381 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05548 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05567 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05573 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05724 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05744 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05747 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05755 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/0603 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/08265 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2225/06524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2225/06565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/30105 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/3011 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
G02B6/12004 (of the integrated circuit kind (electric integrated circuits): 1 patents
H01L23/538 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2924/182 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L24/03 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/0219 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/03011 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05618 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05647 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/05684 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/80379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
G02B27/0172 (Head-up displays): 1 patents
G02B27/102 (OPTICAL ELEMENTS, SYSTEMS OR APPARATUS): 1 patents
G02B27/141 (OPTICAL ELEMENTS, SYSTEMS OR APPARATUS): 1 patents
H01L25/0753 (the devices being of a type provided for in group): 1 patents
G02B2027/0178 (OPTICAL ELEMENTS, SYSTEMS OR APPARATUS): 1 patents
H01L21/565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L21/76819 ({Smoothing of the dielectric (planarisation of insulating materials per se): 1 patents
H01L21/76877 ({Thin films associated with contacts of capacitors}): 1 patents
H01L21/82 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
H01L23/3107 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
H01L2224/02379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L23/473 (by flowing liquids {(): 1 patents
H01L23/367 (Cooling facilitated by shape of device {(): 1 patents
H01L23/49872 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
H01L21/4857 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
H01L23/46 (involving the transfer of heat by flowing fluids (): 1 patents
H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 1 patents
H01L23/4336 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/32225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
H01L2224/80805 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents