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Category:Guilian Gao of Campbell CA (US) - WikiTrademarks Jump to content

Category:Guilian Gao of Campbell CA (US)

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Revision as of 03:37, 29 July 2024 by Unknown user (talk) (Updating Category:Guilian_Gao_of_Campbell_CA_(US))

Guilian Gao of Campbell CA (US)

Executive Summary

Guilian Gao of Campbell CA (US) is an inventor who has filed 4 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (2 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (2 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (3 patents), Adeia Semiconductor Bonding Technologies Inc. (1 patents). Their most frequent collaborators include (2 collaborations), (2 collaborations), (2 collaborations).

Patent Filing Activity

File:Guilian Gao of Campbell CA (US) Monthly Patent Applications.png

Technology Areas

File:Guilian Gao of Campbell CA (US) Top Technology Areas.png

List of Technology Areas

  • H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L24/03 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/46 (involving the transfer of heat by flowing fluids (): 1 patents
  • H01L23/053 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/38 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/08245 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/83 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/6836 ({Wafer tapes, e.g. grinding or dicing support tapes (adhesive tapes in general): 1 patents
  • H01L21/78 (with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 1 patents
  • H01L24/09 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/33 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/98 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2221/68327 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2221/68368 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2221/68381 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/03002 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/09181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/32145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/33181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/83009 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/83896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/83948 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents
  • H01L2224/03462 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/03616 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/05147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2924/3512 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/76898 ({formed through a semiconductor substrate}): 1 patents
  • H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
  • H01L23/5385 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
  • H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
  • H01L24/95 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

File:Guilian Gao of Campbell CA (US) Top Companies.png

List of Companies

  • ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.: 3 patents
  • Adeia Semiconductor Bonding Technologies Inc.: 1 patents

Collaborators

Subcategories

This category has the following 8 subcategories, out of 8 total.

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