Category:Lawrence A. Clevenger of Saratoga Springs NY (US)

Lawrence A. Clevenger of Saratoga Springs NY (US)

Executive Summary

Lawrence A. Clevenger of Saratoga Springs NY (US) is an inventor who has filed 15 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (8 patents), Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor} (5 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), and they have worked with companies such as International Business Machines Corporation (8 patents), INTERNATIONAL BUSINESS MACHINES CORPORATION (7 patents). Their most frequent collaborators include (14 collaborations), (13 collaborations), (5 collaborations).

Patent Filing Activity

File:Lawrence A. Clevenger of Saratoga Springs NY (US) Monthly Patent Applications.png

Technology Areas

File:Lawrence A. Clevenger of Saratoga Springs NY (US) Top Technology Areas.png

List of Technology Areas

• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 8 patents
• H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 5 patents
• H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L27/088 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/564 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/585 ({comprising conductive layers or plates or strips or rods or rings (): 3 patents
• H01L23/60 (Protection against electrostatic charges or discharges, e.g. Faraday shields): 3 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 3 patents
• H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 3 patents
• H01L21/823475 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 2 patents
• H01L21/76804 ({by forming tapered via holes}): 2 patents
• H01L21/76898 ({formed through a semiconductor substrate}): 2 patents
• H01L23/528 ({Geometry or} layout of the interconnection structure {(): 2 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/76816 ({Aspects relating to the layout of the pattern or to the size of vias or trenches (layout of the interconnections per se): 2 patents
• H01L23/5256 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/41725 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/41733 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823418 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823468 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/6656 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/14 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5223 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/768 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/19041 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors): 1 patents
• H10D30/014 (No explanation available): 1 patents
• H10D30/43 (No explanation available): 1 patents
• H10D30/6729 (No explanation available): 1 patents
• H10D30/6735 (No explanation available): 1 patents
• H10D30/6757 (No explanation available): 1 patents
• H10D62/121 (No explanation available): 1 patents
• H10D84/017 (No explanation available): 1 patents
• H10D84/0186 (No explanation available): 1 patents
• H10D84/038 (No explanation available): 1 patents
• H10D84/85 (No explanation available): 1 patents
• H01L21/76229 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers}): 1 patents
• H01L21/76805 ({the opening being a via or contact hole penetrating the underlying conductor}): 1 patents
• H01L23/62 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/7682 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/76838 ({characterised by the formation and the after-treatment of the conductors (etching for patterning the conductors): 1 patents
• H10D84/811 (No explanation available): 1 patents
• H01L23/5228 ({Resistive arrangements or effects of, or between, wiring layers (other resistive arrangements): 1 patents
• H10D1/474 (No explanation available): 1 patents
• H01L27/0928 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

File:Lawrence A. Clevenger of Saratoga Springs NY (US) Top Companies.png

List of Companies

• International Business Machines Corporation: 8 patents
• INTERNATIONAL BUSINESS MACHINES CORPORATION: 7 patents

Collaborators

• Ruilong Xie of Niskayuna NY (US) (14 collaborations)
• Brent A. Anderson of Jericho VT (US) (13 collaborations)
• Albert M. Chu of Nashua NH (US) (5 collaborations)
• Nicholas Anthony Lanzillo of Wynantskill NY (US) (5 collaborations)
• Nicholas Alexander POLOMOFF of Hopewell Junction NY (US) (4 collaborations)
• Matthew Stephen Angyal of Stormville NY (US) (4 collaborations)
• Kisik Choi of Watervliet NY (US) (4 collaborations)
• Terence Hook of Jericho Center VT (US) (4 collaborations)
• LEI ZHUANG of Ridgefield CT (US) (4 collaborations)
• FEE LI LIE of Albany NY (US) (3 collaborations)
• Reinaldo Vega of Mahopac NY (US) (3 collaborations)
• JENS HAETTY of Halfmoon NY (US) (3 collaborations)
• Christopher Murphy of Red Hook NY (US) (3 collaborations)
• Dan Moy of Bethel CT (US) (2 collaborations)
• HUIMEI ZHOU of Albany NY (US) (1 collaborations)
• Min Gyu Sung of Latham NY (US) (1 collaborations)
• FEE LI LIE of ALBANY NY (US) (1 collaborations)
• Nicholas Alexander Polomoff of Hopewell Junction NY (US) (1 collaborations)
• Yann Mignot of Slingerlands NY (US) (1 collaborations)
• Albert M Chu of Nashua NH (US) (1 collaborations)
• Xiaoming Yang of Clifton Park NY (US) (1 collaborations)
• Huai Huang of Clifton Park NY (US) (1 collaborations)
• Hosadurga Shobha of Niskayuna NY (US) (1 collaborations)
• Atharv Jog of Albany NY (US) (1 collaborations)
• Takashi Ando of Eastchester NY (US) (1 collaborations)
• David Wolpert of Poughkeepsie NY (US) (1 collaborations)