Category:John D. Hopkins of Meridian ID (US)

John D. Hopkins of Meridian ID (US)

Executive Summary

John D. Hopkins of Meridian ID (US) is an inventor who has filed 25 patents. Their primary areas of innovation include ELECTRONIC MEMORY DEVICES (14 patents), ELECTRONIC MEMORY DEVICES (14 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (9 patents), and they have worked with companies such as Micron Technology, Inc. (25 patents). Their most frequent collaborators include (11 collaborations), (10 collaborations), (3 collaborations).

Patent Filing Activity

File:John D. Hopkins of Meridian ID (US) Monthly Patent Applications.png

Technology Areas

File:John D. Hopkins of Meridian ID (US) Top Technology Areas.png

List of Technology Areas

• H10B43/27 (ELECTRONIC MEMORY DEVICES): 14 patents
• H10B41/27 (ELECTRONIC MEMORY DEVICES): 14 patents
• H01L27/11582 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 9 patents
• H10B43/35 (ELECTRONIC MEMORY DEVICES): 5 patents
• H01L27/11556 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H10B41/35 (ELECTRONIC MEMORY DEVICES): 4 patents
• H10B41/10 (ELECTRONIC MEMORY DEVICES): 4 patents
• H10B43/10 (ELECTRONIC MEMORY DEVICES): 4 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H10B41/41 (ELECTRONIC MEMORY DEVICES): 3 patents
• H10B43/40 (ELECTRONIC MEMORY DEVICES): 3 patents
• G11C16/0483 ({comprising cells having several storage transistors connected in series}): 3 patents
• H01L23/535 (including internal interconnections, e.g. cross-under constructions {(internal lead connections): 3 patents
• H01L27/11565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L27/1157 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• G11C5/06 (STATIC STORES (semiconductor memory devices): 2 patents
• H01L29/40117 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/28518 (from a gas or vapour, e.g. condensation): 2 patents
• H01L27/11524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H10B41/50 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10B43/50 (ELECTRONIC MEMORY DEVICES): 2 patents
• H01L27/11519 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/2254 ({from or through or into an applied layer, e.g. photoresist, nitrides}): 1 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/31053 ({involving a dielectric removal step}): 1 patents
• H01L21/31144 ({using masks}): 1 patents
• H01L21/76224 ({using trench refilling with dielectric materials (trench filling with polycristalline silicon): 1 patents
• H01L29/40114 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/42328 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/42344 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76895 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/76805 ({the opening being a via or contact hole penetrating the underlying conductor}): 1 patents
• H01L21/76829 ({characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}): 1 patents
• H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/76889 ({by deposition over sacrificial masking layer, e.g. lift-off (lift-off per se): 1 patents
• H01L27/11553 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• G11C5/025 ({Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits,): 1 patents
• H01L21/768 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/31111 ({by chemical means}): 1 patents
• H01L21/31155 (Doping the insulating layers): 1 patents
• H01L21/32134 ({by liquid etching only}): 1 patents
• H01L21/32155 (Doping the layers): 1 patents
• H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L21/30608 ({Anisotropic liquid etching (): 1 patents
• H01L21/3086 ({characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment}): 1 patents
• H01L27/11578 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L27/11543 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

File:John D. Hopkins of Meridian ID (US) Top Companies.png

List of Companies

• Micron Technology, Inc.: 25 patents

Collaborators

• Alyssa N. Scarbrough of Boise ID (US) (11 collaborations)
• Jordan D. Greenlee of Boise ID (US) (10 collaborations)
• Darwin A. Clampitt of Wilder ID (US) (3 collaborations)
• Nancy M. Lomeli of Boise ID (US) (3 collaborations)
• Shuangqiang Luo of Boise ID (US) (2 collaborations)
• Matthew J. King of Boise ID (US) (1 collaborations)
• Roger W. Lindsay of Boise ID (US) (1 collaborations)
• Kevin Y. Titus of Meridian ID (US) (1 collaborations)
• Rohit Kothari of Boise ID (US) (1 collaborations)
• Adam L. Olson of Boise ID (US) (1 collaborations)
• Jeslin J. Wu of Boise ID (US) (1 collaborations)
• Sidhartha Gupta of Boise ID (US) (1 collaborations)
• Adam W. Saxler of Boise ID (US) (1 collaborations)
• Andrew Li of Boise ID (US) (1 collaborations)
• Andrew L. Li of Boise ID (US) (1 collaborations)
• Michael J. Puett of Boise ID (US) (1 collaborations)
• Christopher R. Ritchie of Boise ID (US) (1 collaborations)
• Lifang Xu of Boise ID (US) (1 collaborations)
• Indra V. Chary of Boise ID (US) (1 collaborations)
• Kar Wui Thong of Boise ID (US) (1 collaborations)
• Shicong Wang of Meridain ID (US) (1 collaborations)