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Category:Varghese George of Folsom CA (US)

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Varghese George of Folsom CA (US)

Executive Summary

Varghese George of Folsom CA (US) is an inventor who has filed 8 patents. Their primary areas of innovation include Processor architectures; Processor configuration, e.g. pipelining (7 patents), for evaluating functions by calculation {( (5 patents), {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} (5 patents), and they have worked with companies such as Intel Corporation (7 patents), INTEL CORPORATION (1 patents). Their most frequent collaborators include (7 collaborations), (6 collaborations), (6 collaborations).

Patent Filing Activity

File:Varghese George of Folsom CA (US) Monthly Patent Applications.png

Technology Areas

File:Varghese George of Folsom CA (US) Top Technology Areas.png

List of Technology Areas

  • G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining): 7 patents
  • G06F7/5443 (for evaluating functions by calculation {(): 5 patents
  • G06F9/30036 ({Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}): 5 patents
  • G06F9/3887 ({controlled by a single instruction for multiple data lanes [SIMD]}): 5 patents
  • G06F12/0875 (with dedicated cache, e.g. instruction or stack): 5 patents
  • G06F12/0891 (using clearing, invalidating or resetting means): 5 patents
  • G06F15/8046 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 5 patents
  • G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition): 5 patents
  • G06T1/60 (Memory management): 5 patents
  • G06F2212/302 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 5 patents
  • G06N3/08 (Learning methods): 5 patents
  • G06F15/7839 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F7/575 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F7/588 (Random or pseudo-random number generators): 4 patents
  • G06F9/3001 ({Arithmetic instructions}): 4 patents
  • G06F9/30014 ({with variable precision}): 4 patents
  • G06F9/3004 ({to perform operations on memory}): 4 patents
  • G06F9/30043 ({LOAD or STORE instructions; Clear instruction}): 4 patents
  • G06F9/30047 ({Prefetch instructions; cache control instructions}): 4 patents
  • G06F9/30079 ({Pipeline control instructions, e.g. multicycle NOP}): 4 patents
  • G06F9/5011 (Allocation of resources, e.g. of the central processing unit [CPU]): 4 patents
  • G06F9/5077 (Allocation of resources, e.g. of the central processing unit [CPU]): 4 patents
  • G06F12/0215 ({with look ahead addressing means}): 4 patents
  • G06F12/0238 ({Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}): 4 patents
  • G06F12/0246 ({in block erasable memory, e.g. flash memory}): 4 patents
  • G06F12/0607 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (): 4 patents
  • G06F12/0802 (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 4 patents
  • G06F12/0804 (with main memory updating (): 4 patents
  • G06F12/0811 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/0862 (with prefetch): 4 patents
  • G06F12/0866 (for peripheral storage systems, e.g. disk cache): 4 patents
  • G06F12/0871 (Allocation or management of cache space): 4 patents
  • G06F12/0882 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/0893 (Caches characterised by their organisation or structure): 4 patents
  • G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/0897 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/1009 (Address translation): 4 patents
  • G06F12/128 (Replacement control): 4 patents
  • G06F17/18 (for evaluating statistical data {, e.g. average values, frequency distributions, probability functions, regression analysis (forecasting specially adapted for a specific administrative, business or logistic context): 4 patents
  • H03M7/46 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 4 patents
  • G06F9/3802 ({Instruction prefetching}): 4 patents
  • G06F9/3818 ({Decoding for concurrent execution}): 4 patents
  • G06F9/3867 ({using instruction pipelines}): 4 patents
  • G06F2212/1021 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/1044 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/401 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/455 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/60 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F9/3888 ({controlled by a single instruction for multiple threads [SIMT] in parallel}): 4 patents
  • G06F9/30065 ({Loop control instructions; iterative instructions, e.g. LOOP, REPEAT}): 3 patents
  • G06T15/06 (Ray-tracing): 3 patents
  • G06F12/0888 (using selective caching, e.g. bypass): 3 patents
  • G06F2212/1008 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 3 patents
  • G06F13/4027 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
  • G06F12/123 (Replacement control): 1 patents
  • G06F9/38885 ({Divergence aspects}): 1 patents
  • G06F9/5027 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
  • G06F12/0806 (Multiuser, multiprocessor or multiprocessing cache systems): 1 patents
  • G06N3/048 (Activation functions): 1 patents
  • G06N3/084 (Backpropagation, e.g. using gradient descent): 1 patents

Companies

File:Varghese George of Folsom CA (US) Top Companies.png

List of Companies

  • Intel Corporation: 7 patents
  • INTEL CORPORATION: 1 patents

Collaborators

Subcategories

This category has the following 8 subcategories, out of 8 total.

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