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Category:Vasanth Ranganathan of El Dorado Hills CA (US)

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Vasanth Ranganathan of El Dorado Hills CA (US)

Executive Summary

Vasanth Ranganathan of El Dorado Hills CA (US) is an inventor who has filed 10 patents. Their primary areas of innovation include {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} (7 patents), Processor architectures; Processor configuration, e.g. pipelining (7 patents), Memory management (7 patents), and they have worked with companies such as Intel Corporation (9 patents), INTEL CORPORATION (1 patents). Their most frequent collaborators include (8 collaborations), (7 collaborations), (7 collaborations).

Patent Filing Activity

File:Vasanth Ranganathan of El Dorado Hills CA (US) Monthly Patent Applications.png

Technology Areas

File:Vasanth Ranganathan of El Dorado Hills CA (US) Top Technology Areas.png

List of Technology Areas

  • G06F9/30036 ({Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}): 7 patents
  • G06T1/20 (Processor architectures; Processor configuration, e.g. pipelining): 7 patents
  • G06T1/60 (Memory management): 7 patents
  • G06F9/3887 ({controlled by a single instruction for multiple data lanes [SIMD]}): 6 patents
  • G06F7/5443 (for evaluating functions by calculation {(): 6 patents
  • G06F17/16 (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition): 6 patents
  • G06N3/08 (Learning methods): 6 patents
  • G06F9/3001 ({Arithmetic instructions}): 5 patents
  • G06F9/30014 ({with variable precision}): 5 patents
  • G06F12/0802 (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 5 patents
  • G06F12/0875 (with dedicated cache, e.g. instruction or stack): 5 patents
  • G06F12/0891 (using clearing, invalidating or resetting means): 5 patents
  • G06F15/8046 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 5 patents
  • G06F2212/302 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 5 patents
  • G06F9/3888 ({controlled by a single instruction for multiple threads [SIMT] in parallel}): 5 patents
  • G06F15/7839 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F7/575 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F7/588 (Random or pseudo-random number generators): 4 patents
  • G06F9/3004 ({to perform operations on memory}): 4 patents
  • G06F9/30043 ({LOAD or STORE instructions; Clear instruction}): 4 patents
  • G06F9/30047 ({Prefetch instructions; cache control instructions}): 4 patents
  • G06F9/30079 ({Pipeline control instructions, e.g. multicycle NOP}): 4 patents
  • G06F9/5011 (Allocation of resources, e.g. of the central processing unit [CPU]): 4 patents
  • G06F9/5077 (Allocation of resources, e.g. of the central processing unit [CPU]): 4 patents
  • G06F12/0215 ({with look ahead addressing means}): 4 patents
  • G06F12/0238 ({Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}): 4 patents
  • G06F12/0246 ({in block erasable memory, e.g. flash memory}): 4 patents
  • G06F12/0607 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (): 4 patents
  • G06F12/0804 (with main memory updating (): 4 patents
  • G06F12/0811 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/0862 (with prefetch): 4 patents
  • G06F12/0866 (for peripheral storage systems, e.g. disk cache): 4 patents
  • G06F12/0871 (Allocation or management of cache space): 4 patents
  • G06F12/0882 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/0893 (Caches characterised by their organisation or structure): 4 patents
  • G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/0897 (in hierarchically structured memory systems, e.g. virtual memory systems): 4 patents
  • G06F12/1009 (Address translation): 4 patents
  • G06F12/128 (Replacement control): 4 patents
  • G06F17/18 (for evaluating statistical data {, e.g. average values, frequency distributions, probability functions, regression analysis (forecasting specially adapted for a specific administrative, business or logistic context): 4 patents
  • H03M7/46 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 4 patents
  • G06F9/3802 ({Instruction prefetching}): 4 patents
  • G06F9/3818 ({Decoding for concurrent execution}): 4 patents
  • G06F9/3867 ({using instruction pipelines}): 4 patents
  • G06F2212/1021 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/1044 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/401 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/455 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F2212/60 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 4 patents
  • G06F9/30065 ({Loop control instructions; iterative instructions, e.g. LOOP, REPEAT}): 3 patents
  • G06T15/06 (Ray-tracing): 3 patents
  • G06F12/0888 (using selective caching, e.g. bypass): 3 patents
  • G06F2212/1008 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 3 patents
  • G06T15/005 ({General purpose rendering architectures}): 2 patents
  • G06F9/3016 ({Decoding the operand specifier, e.g. specifier format}): 1 patents
  • G06T17/20 (Finite element generation, e.g. wire-frame surface description, {tesselation}): 1 patents
  • G06F7/483 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
  • G06F9/3851 ({from multiple instruction streams, e.g. multistreaming}): 1 patents
  • G06N3/044 (Recurrent networks, e.g. Hopfield networks): 1 patents
  • G06N3/045 (Combinations of networks): 1 patents
  • G06N3/063 (using electronic means): 1 patents
  • G09G5/393 (ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays): 1 patents
  • G06F1/16 (Constructional details or arrangements): 1 patents
  • G06F9/30025 ({Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion}): 1 patents
  • G06F9/3013 ({according to data content, e.g. floating-point registers, address registers}): 1 patents
  • G06F2207/3824 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
  • G06N20/00 (Machine learning): 1 patents
  • G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 1 patents
  • G06F2212/70 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
  • G06F12/123 (Replacement control): 1 patents
  • G06F9/38885 ({Divergence aspects}): 1 patents
  • G06F9/5027 (Allocation of resources, e.g. of the central processing unit [CPU]): 1 patents
  • G06F12/0806 (Multiuser, multiprocessor or multiprocessing cache systems): 1 patents
  • G06N3/048 (Activation functions): 1 patents
  • G06N3/084 (Backpropagation, e.g. using gradient descent): 1 patents

Companies

File:Vasanth Ranganathan of El Dorado Hills CA (US) Top Companies.png

List of Companies

  • Intel Corporation: 9 patents
  • INTEL CORPORATION: 1 patents

Collaborators

Subcategories

This category has the following 10 subcategories, out of 10 total.

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